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5.2.1.1 Pin configuration options
The IRQ pin enable control bit (IRQSC[IRQPE]) must be 1 for the IRQ pin to act as the
IRQ input. The user can choose the polarity of edges or levels detected (IRQEDG),
whether the pin detects edges-only or edges and levels (IRQMOD), or whether an event
causes an interrupt or only sets the IRQF flag, which can be polled by software.
When enabled, the IRQ pin defaults to use an internal pullup device (IRQSC[IRQPDD] =
0). If the user uses an external pullup or pulldown, the IRQSC[IRQPDD] can be written
to a 1 to turn off the internal device.
BIH and BIL instructions may be used to detect the level on the IRQ pin when it is
configured to act as the IRQ input.
Note
This pin does not contain a clamp diode to V
DD
and must not be
driven above V
DD
. The voltage measured on the internally
pullup IRQ pin may be as low as V
DD
– 0.7 V. The internal
gates connected to this pin are pulled all the way to V
DD
.
When enabling the IRQ pin for use, the IRQF will be set, and
must be cleared prior to enabling the interrupt. When
configuring the pin for falling edge and level sensitivity in a 3
V system, it is necessary to wait at least cycles between
clearing the flag and enabling the interrupt.
5.2.1.2 Edge and level sensitivity
The IRQSC[IRQMOD] control bit reconfigures the detection logic so that it can detect
edge events and pin levels. In this detection mode, the IRQF status flag is set when an
edge is detected, if the IRQ pin changes from the de-asserted to the asserted level, but the
flag is continuously set and cannot be cleared as long as the IRQ pin remains at the
asserted level.
Interrupt pin request register
IRQ memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
3B
Interrupt Pin Request Status and Control Register (IRQ_SC)
8
R/W
00h
5.3
Chapter 5 Interrupt
MC9S08PA4 Reference Manual, Rev. 5, 08/2017
NXP Semiconductors
107
Содержание MC9S08PA4
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Страница 28: ...System clock distribution MC9S08PA4 Reference Manual Rev 5 08 2017 28 NXP Semiconductors ...
Страница 150: ...Port data registers MC9S08PA4 Reference Manual Rev 5 08 2017 150 NXP Semiconductors ...
Страница 196: ...Human machine interfaces HMI MC9S08PA4 Reference Manual Rev 5 08 2017 196 NXP Semiconductors ...
Страница 224: ...Instruction Set Summary MC9S08PA4 Reference Manual Rev 5 08 2017 224 NXP Semiconductors ...
Страница 232: ...Functional Description MC9S08PA4 Reference Manual Rev 5 08 2017 232 NXP Semiconductors ...
Страница 258: ...FTM Interrupts MC9S08PA4 Reference Manual Rev 5 08 2017 258 NXP Semiconductors ...
Страница 268: ...Initialization application information MC9S08PA4 Reference Manual Rev 5 08 2017 268 NXP Semiconductors ...
Страница 294: ...Functional description MC9S08PA4 Reference Manual Rev 5 08 2017 294 NXP Semiconductors ...
Страница 370: ...Memory map and register description MC9S08PA4 Reference Manual Rev 5 08 2017 370 NXP Semiconductors ...
Страница 398: ...Resets MC9S08PA4 Reference Manual Rev 5 08 2017 398 NXP Semiconductors ...
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