NXP Semiconductors MC9S08PA4, Справочное руководство

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Channel (n) - high-true EPWM
FTM counter
0
3 4 0 1 2 3 4 0 1 2 3 4 0 1 2
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
prescaler counter
channel (n) output
counter
overflow
channel (n)
match
counter
overflow
channel (n)
match
channel (n)
match
counter
overflow
PS[2:0] = 001
MODH:L = 0x0004
CnVH:L = 0x0002
Figure 12-2. Notation used
12.4.1 Clock Source
FTM module has only one clock domain that is the system clock.
12.4.1.1 Counter Clock Source
The CLKS[1:0] bits in the SC register select one of three possible clock sources for the
FTM counter or disable the FTM counter. After any MCU reset, CLKS[1:0] = 0:0 so no
clock source is selected.
The CLKS[1:0] bits may be read or written at any time. Disabling the FTM counter by
writing 0:0 to the CLKS[1:0] bits does not affect the FTM counter value or other
registers.
The fixed frequency clock is an alternative clock source for the FTM counter that allows
the selection of a clock other than the system clock or an external clock. This clock input
is defined by chip integration. Refer to chip specific documentation for further
information. Due to FTM hardware implementation limitations, the frequency of the
fixed frequency clock must not exceed the system clock frequency.
The external clock passes through a synchronizer clocked by the system clock to ensure
that counter transitions are properly aligned to system clock transitions. Therefore, to
meet the Nyquist criteria and account for jitter, the frequency of the external clock source
must not exceed 1/4 of the system clock frequency.
Chapter 12 FlexTimer Module (FTM)
MC9S08PA4 Reference Manual, Rev. 5, 08/2017
NXP Semiconductors 245