NXP Semiconductors MC9S08PA4, Справочное руководство

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The following figure shows the host receiving a logic 0 from the target HCS08 MCU.
Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from
the host-generated falling edge on BKGD to the start of the bit time as perceived by the
target MCU. The host initiates the bit time but the target HCS08 finishes it. Because the
target wants the host to receive a logic 0, it drives the BKGD pin low for 13 BDC clock
cycles, then briefly drives it high to speed up the rising edge. The host samples the bit
level about 10 cycles after starting the bit time.
10 C Y C LE S
B D C C LO C K
(T A R G E T M C U )
H O S T D R IV E
T O B K G D P IN
T A R G E T M C U
D R IV E A N D
P E R C E IV E D S T A R T
O F B IT T IM E
H IG H -IM P E D A N C E
B K G D P IN
10 C Y C LE S
S P E E D -U P P U LS E
S P E E D U P
P U LS E
E A R LIE S T S TA R T
O F N E X T B IT
H O S T S A M P LE S B K G D P IN
Figure 18-4. BDM target-to-host serial bit timing (logic 0)
18.2.3 BDC commands
BDC commands are sent serially from a host computer to the BKGD pin of the target
HCS08 MCU. All commands and data are sent MSB-first using a custom BDC
communications protocol. Active background mode commands require that the target
MCU is currently in the active background mode while non-intrusive commands may be
issued at any time whether the target MCU is in active background mode or running a
user application program.
The following table shows all HCS08 BDC commands, a shorthand description of their
coding structure, and the meaning of each command.
Coding Structure Nomenclature
This nomenclature is used in the following table to describe the coding structure of the
BDC commands.
Background debug controller (BDC)
MC9S08PA4 Reference Manual, Rev. 5, 08/2017
356 NXP Semiconductors