M5253EVBE Users Manual, Rev. 1
Freescale Semiconductor
3-9
connected, although both cannot be supported simultaneously, as the IDE-DIOR and IDE-DIOW signals
can only be used to interface to one or the other.
3.7
ATA Interface Module
The MCF5253 processor’s ATA interface module includes the following features:
•
Programmable timing on the ATA bus. The interface works with wide range of bus frequencies.
•
Compliance with ATA-6 specification
— Support for PIO modes 0, 1, 2, 3, and 4
— Support for multiword DMA modes 0, 1, and 2
— Support for ultra DMA modes 0, 1, 2, 3, and 4 with bus clock of at least 50 MHz
— Support for ultra DMA mode 5 with bus clock of at least 80 MHz
•
128-byte FIFO part of interface
•
FIFO receive alarm and FIFO transmit alarm to DMA unit
•
Zero-wait cycles transfer between DMA bus and FIFO, which allows fast FIFO reading and
writing
3.8
Real-Time Clock (RTC) Module
The MCF5253 processor's RTC module is a mixed-signal circuit that provides an indicator of time (in
seconds) for various purposes in the system. The MCF5253 processor’s RTC module includes the
following features:
•
32.768 kHz crystal
•
Independent power supply pins to allow battery backup operation
•
Circuitry to detect power supply tampering
3.9
Debug Connector J12
The MCF5253 processor has a Background Debug Mode (BDM) port, which supports real-time trace and
real-time debug. The signals which are necessary for debug are available at connector (J12).
Figure 3-1
shows the (J12) connector pin assignment.