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M5253EVBE Users Manual, Rev. 1
1-4
Freescale Semiconductor
There is one SDRAM (U12) device on the PCB. The system ships with 1 x 4 Mbytes x 16 of SDRAM
totalling 8 Mbytes of volatile memory.
The internal cache of the MCF5253 is non-blocking. The instruction cache is 8 Kbytes with a 16-byte line
size. The ROM monitor currently does not utilize the cache, but programs downloaded with the ROM
monitor can initialize and use the cache.
1.3
Serial Communication Channels
The MCF5253 processor has 3 built-in UARTs with independent baud rate generators. The signals of all
channels can be passed through the external transceiver to make the channels RS-232 compatible (P4). An
RS-232 serial cable with DB9 connectors is included with the board. UART0 channel is the “TERMINAL”
channel used by dBUG for communication with an external terminal/PC. The “TERMINAL” baud rate
defaults to 115200.
1.4
Parallel I/O Ports
The MCF5253 offers up to 60 lines of general-purpose I/O, of which six are dedicated inputs and three are
dedicated outputs. Seven of the GPIO lines are also available as edge-sensitive interrupt inputs. In
addition, there is one dedicated input for wake-up from low-power mode.
1.5
System Configuration
The M5253EVBE board requires the following items for minimum system configuration:
•
The M5253EVBE board (provided)
•
Power supply, +7 V to 14 V DC with minimum of 1.0 amp
•
RS232C-compatible terminal or a PC with terminal emulation software
•
RS232 communication cable (provided)
Refer to
Section 2.2.2, “System Initialization
” for initial system setup.