M5253EVBE Users Manual, Rev. 1
Freescale Semiconductor
3-5
chip-select zero (CS0) responds to any accesses after reset until the CSMR0 is written. Since CS0 (the
global chip select) is connected to the Flash ROM (U11), the Flash ROM initially appears at address
0x0000_0000 which provides the initial stack pointer and program counter (the first eight bytes of the
Flash ROM). The initialization routine then programs the chip-select logic, locates the Flash ROM to start
at 0xFFE0_0000, and configures the rest of the internal and external peripherals.
3.1.10
TA Generation
The processor starts a bus cycle by asserting CS
x
with the other control signals. The processor then waits
for a transfer acknowledgment (TA) either from within (auto acknowledge—AA mode) or from the
externally addressed device before it can complete the bus cycle. TA is used to indicate the completion of
the bus cycle. It also allows devices with different access times to communicate with the processor
properly (that is, asynchronously). The MCF5253 processor, as part of the chip-select logic, has a built-in
mechanism to generate TA for all external devices which do not have the capability to generate this signal.
For example the Flash ROM cannot generate a TA signal. The chip-select logic is programmed by the
dBUG ROM monitor to generate TA internally after a pre-programmed number of wait states.
3.1.11
Wait State Generator
The Flash ROM and SDRAM on the board may require some adjustments to the cycle time of the
processor to make them compatible with the processor’s external bus speed. To extend the CPU bus cycles
for the slower devices, the chip-select logic of the MCF5253 processor can be programmed to generate an
internal TA after a given number of wait states. See
Table 3-1
for information about the address space of
the memory and refer to the manufacturer’s specification for wait state requirements of the SDRAM and
Flash ROM.
3.1.12
SDRAM
The M5253EVBE has one 64-Mbit device on the board, in a 16-bit wide data bus configuration. The
MCF5253 processor supports one bank of SDRAM, which on this board is represented by SDRAM
device, (U12). These are connected to the MCF5253 to provide 4Mx16 of memory.
3.1.13
Flash ROM
There is one 2-Mbyte Flash ROM on the M5253EVBE, (U11).
The board is shipped with one AMD AM29LV160DB, 2-Mbyte Flash ROM. The first 256 Kbytes of the
Flash contains the ROM Monitor firmware dBUG. The remaining Flash memory is available to the user.
The MCF5253 chip-select logic can be programmed to generate the TA for CS0 signal after a certain
number of wait states (that is, auto-acknowledge mode). The dBUG monitor programs this parameter to
be six wait-states.
3.2
Serial Communication Channels
The M5253EVBE offers five types of serial communications channels. They are discussed in this section.