M5253EVBE Users Manual, Rev. 1
Freescale Semiconductor
3-3
The MCF5253 microprocessor has seven external interrupt request lines INT[6:0], all of which are
multiplexed with other functions. The interrupt controller is capable of providing up to 75 interrupt
sources. These sources include:
•
External interrupt signals INT[6:0]
•
Software watchdog timer module
•
Two general purpose timer modules
•
UART module
•
I
2
C module
•
Audio interface modules
•
DMA module
•
QSPI module
•
CAN module
•
USB module
•
ATA module
•
Flash media module
All external interrupt inputs are edge sensitive. The active level is programmable. An interrupt request
must be held valid until an IACK cycle starts to guarantee correct processing. Each interrupt input can have
its priority programmed by setting the xIPL[2:0] bits in the Interrupt Control Registers.
NOTE
No interrupt sources should have the same level and priority as another.
Programming two interrupt sources with the same level and priority can
result in undefined operation.
The M5253EVBE hardware uses INT1 to support the ABORT function using the ABORT switch (S2).
This switch is used to force an interrupt (level 7, priority 3) if the user's program execution should be
aborted without issuing a RESET command. See
Section 2.2.2.2, “ABORT Button,”
for more information
on ABORT.) Since the ABORT switch is not capable of generating a vector in response to a level seven
interrupt acknowledge from the processor, the dBUG programs this interrupt request for autovector mode.
3.1.7
Internal SRAM
The MCF5253 processor has 128 Kbtyes of internal memory which may be programmed as data or
instruction memory. This memory is mapped to 0x2000_0000 and configured as data space but is not used
by the dBUG monitor except during system initialization. After system initialization is complete, the
internal memory is available to the user. The memory can be relocated to any 32-Kbyte boundary.
3.1.8
MCF5253 Registers and Memory Map
The memory and I/O resources of the M5253EVBE hardware are divided into two groups, MCF5253
internal and external resources. All the I/O registers are memory mapped.