M5253EVBE Users Manual, Rev. 1
3-6
Freescale Semiconductor
3.2.1
UARTs
The MCF5253 device has three built-in UARTs, each with its own software programmable baud rate
generator. UART0 is the ROM Monitor to Terminal output. The ROM Monitor programs the interrupt
level for UART0 to Level 3, priority 2 and autovector mode of operation.
3.2.2
QSPI Module
The QSPI (Queued Serial Peripheral Interface) module provides a serial peripheral interface with queued
transfer capability. It will support up to 16 stacked transfers at one time, minimizing CPU intervention
between transfers. Transfer RAMs in the QSPI are indirectly accessible using address and data registers.
Functionality is very similar, but not identical, to the QSPI portion of the QSM (Queued Serial Module)
implemented in the MC68332 processor.
•
Programmable queue to support up to 16 transfers without user intervention
•
Supports transfer sizes of 8 to 16 bits in 1-bit increments
•
Four peripheral chip-select lines for control of up to 15 devices
•
Baud rates from 274.5 Kbps to 17.5 Mbps at 140 MHz.
•
Programmable delays before and after transfers
•
Programmable clock phase and polarity
•
Supports wrap-around mode for continuous transfers
The QSPI signals from the MCF5253 device are brought out to connector (J5). Some of these signals are
multiplexed with other functions.
3.2.3
I
2
C Modules
The MCF5253 processor’s two I
2
C modules include the following features:
•
Compatibility with the I
2
C bus standard
•
Multimaster operation
•
Software programmable for one of 64 different clock frequencies
•
Software selectable acknowledge bit
•
Interrupt driven byte by byte data transfer
•
Arbitration-lost interrupt with auto mode switching from master to slave
•
Calling address identification interrupt
•
Start and stop signal generation and detection
•
Repeated start signal generation
•
Acknowledge bit generation and detection
•
Bus busy detection
3.2.4
FlexCAN Modules
The MCF5253 processor’s two FlexCAN modules includes the following features: