M5253EVBE Users Manual, Rev. 1
Freescale Semiconductor
3-1
Chapter 3
Hardware Description and Reconfiguration
This chapter provides a functional description of the M5253EVBE board hardware. With the description
given here and the schematic diagrams in
Appendix A, “Schematics,”
the user can gain a good
understanding of the board's design. In this manual, an active low signal is indicated by a bar over the
signal name.
3.1
Processor and Support Logic
This part of the chapter discusses the CPU and general support logic on the M5253EVBE board. See the
MCF5253 Reference Manual
for more detailed information.
3.1.1
Processor
The microprocessor used on the M5253EVBE is the highly integrated ColdFire® MCF5253, 32-bit
processor. The MCF5253 implements a Version 2 ColdFire core with 8-Kbyte instruction cache, three
UART channels, two timers, 128-Kbytes of SRAM, a QSPI (Queued Serial Peripheral Interface) module,
two I
2
C modules, three I
2
S modules, an IDE module, a dedicate ATA interface with DMA support, two
FlexCAN modules, an OTG USB 2.0 controller with integrated physical interface, real time clock (RTC),
a Flash memory stick interface, 60 parallel I/O ports (which are multiplexed with other signals) and the
system integration module (SIM). All of the core processor registers are 32 bits wide except for the status
register (SR) which is 16 bits wide. This processor communicates with external devices over a 16-bit wide
data bus, D[31:16]. The chip can address 64 Mbytes of memory space using a 25-bit wide address bus and
internal chip-select logic.
The MCF5253 processor has the capability to support both an IEEE JTAG-compatible port and a BDM
debug port. These ports are multiplexed and can be used with third party tools to allow the user to
download code to the board. The board is configured to boot up in the normal/BDM mode of operation.
The BDM signals are available at port (J12). The processor also has the logic to generate up to four (4)
chip selects, and support for a bank of SDRAM (included on the evaluation board as 8 Mbytes in total
configured as 4 M x 16). The SDRAM_CS1 signal is used to provide selection and control of this bank of
SDRAM.
3.1.2
Reset Logic
The reset logic provides system initialization. Reset occurs during power-on or via assertion of the signal
RESET which causes the MCF5253 to reset. Reset is also triggered by the reset switch (S1) which resets
the entire processor/system.
A hard reset and voltage sense controller (U18) is used to produce an active low power-on RESET signal.
The reset switch S1 is fed into U18 which generates the signal which is fed to the MCF5253 reset, RESET.