M5253EVBE Users Manual, Rev. 1
Freescale Semiconductor
2-3
Figure 2-1 Flow Diagram of dBUG Operational Mode
2.2.2
System Initialization
The act of powering up the board will initialize the system. The processor is reset and dBUG is invoked.
dBUG performs the following configurations of internal resources during the initialization. The instruction
cache is invalidated and disabled. The Vector Base Register (VBR) points to the Flash. However, a copy
of the exception table is made at address 0x0000_0000 in SDRAM. To take over an exception vector, the
user places the address of the exception handler in the appropriate vector in the vector table located at
0x0000_0000, and then points the VBR to 0x0000_0000.
The Software Watchdog Timer is disabled and internal timers are placed in a stop condition. Interrupt
controller registers initialized with unique interrupt level/priority pairs. Refer to the dBUG source files on
the ColdFire website (
http://www.freescale.com/coldfire
) for the complete initialization code sequence.
After initialization, the terminal displays the following:
Hard Reset
DRAM Size: 8M
ColdFire MCF5253 on the M5253EVB
Firmware v4c.1b.1a (Built on Feb 1 2007 11:45:04)
Copyright 2006 Freescale Semiconductor, Inc.
Enter 'help' for help.
dBUG>
Command Line
Input from
Terminal?
Does
Line Cause User
Program
Execution?
Command
Execute
Function
Command
Initialize
No
Yes
No
Yes
Jump to User
Program and
Begin Execution