MS51
Dec. 17, 2019
Page
33
of 316
Rev 1.01
M
S51
SE
RIES
TE
CHNICA
L REF
ERE
N
CE MA
NU
A
L
TA
– Timed Access
7
6
5
4
3
2
1
0
TA[7:0]
W
Address: C7H, all pages Reset value: 0000 0000b
Bit
Name
Description
7:0
TA[7:0]
Timed access
The timed access register controls the access to protected SFR. To access protected bits, user
should first write AAH to the TA and immediately followed by a write of 55H to TA. After these two
steps, a writing permission window is opened for 4 clock cycles during this period that user may
write to protected SFR.
In timed access method, the bits, which are protected, have a timed write enable window. A write is
successful only if this window is active, otherwise the write will be discarded. When the software writes
AAH to TA, a counter is started. This counter waits for 3 clock cycles looking for a write of 55H to TA.
If the second write of 55H occurs within 3 clock cycles of the first write of AAH, then the timed access
window is opened. It remains open for 4 clock cycles during which user may write to the protected bits.
After 4 clock cycles, this window automatically closes. Once the window closes, the procedure should
be repeated to write another protected bits. Not that the TA protected SFR are required timed access
for writing but reading is not protected. User may read TA protected SFR without giving AAH and 55H
to TA register. The suggestion code for opening the timed access window is shown below.
(CLR EA)
;if any interrupt is enabled, disable temporally
MOV TA,#0AAH
MOV TA,#55H
(Instruction that writes a TA protected register)
(SETB EA)
;resume interrupts enabled
Any enabled interrupt should be disabled during this procedure to avoid delay between these three
writings. If there is no interrupt enabled, the
CLR EA
and
SETB EA
instructions can be left out.
Examples of timed assess are shown to illustrate correct or incorrect writing process.
Example 1,
MOV TA,#0AAH
;3 clock cycles
MOV TA,#55H
;3 clock cycles
ORL WDCON,#data
;4 clock cycles
Example 2,
MOV TA,#0AAH
;3 clock cycles
MOV TA,#55H
;3 clock cycles
NOP
;1 clock cycle
ANL BODCON0,#data
;4 clock cycles
Example 3,
MOV TA,#0AAH
;3 clock cycles
MOV TA,#55H
;3 clock cycles
MOV WDCON,#data1
;3 clock cycles
ORL BODCON0,#data2
;4 clock cycles
Example 4,
MOV TA,#0AAH
;3 clock cycles
NOP
;1 clock cycle
MOV TA,#55H
;3 clock cycles