MS51
Dec. 17, 2019
Page
159
of 316
Rev 1.01
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S51
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RIES
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CHNICA
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Power-Down Mode
6.2.2.2
Power-down mode is the lowest power state that the MS51 can enter. It remain the power
consumption as A ”Μa” level by stopping the system clock source. Both of CPU and peripheral
functions like Timers or UART are frozen. Flash memory is put into its stop mode. All activity is
completely stopped and the power consumption is reduced to the lowest possible value. The device
can be put into Power-down mode by writing 1 to bit PD (PCON.1). The instruction that does this
action will be the last instruction to be executed before the device enters Power-down mode. In the
Power-down mode, RAM maintains its content. The port pins output the values held by their own state
before Power-down respectively.
There are several ways to exit the MS51 from the Power-down mode. The first is with all resets except
software reset. Brown-out reset will also wake up CPU from Power-down mode. Be sure that brown-
out detection is enabled before the system enters Power-down. However, for least power
consumption, it is recommended to enable low power BOD in Power-down mode. Of course the
external pin reset and power-on reset will remove the Power-down status. After the external reset or
power-on reset. The CPU is initialized and start executing program code from the beginning.
The second way to wake the MS51 up from the Power-down mode is by an enabled external interrupt.
The trigger on the external pin will asynchronously restart the system clock. After oscillator is stable,
the device executes the interrupt service routine (ISR) for the corresponding external interrupt. After
the ISR is completed, the program execution returns to the instruction after the one, which puts the
device into Power-down mode and continues. Interrupts that allows to wake up CPU from Power-down
mode includes external interrupt
INT0
̅̅̅̅̅̅̅
and
INT1
̅̅̅̅̅̅̅
, pin interrupt, WDT interrupt, WKT interrupt, and
brown-out interrupt.
PCON
– Power Control
Regiser
Address
Reset Value
PCON
87H, all pages
POR, 0001_0000b
Others,000U_0000b
7
6
5
4
3
2
1
0
SMOD
SMOD0
-
POF
GF1
GF0
PD
IDL
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
Bit
Name
Description
1
PD
Power-down mode
Setting this bit puts CPU into Power-down mode. Under this mode, both CPU and peripheral clocks
stop and Program Counter (PC) suspends. It provides the lowest power consumption. After CPU is
woken up from Power-down, this bit will be automatically cleared via hardware and the program
continue executing the interrupt service routine (ISR) of the very interrupt source that woke the
system up before. After return from the ISR, the device continues execution at the instruction, which
follows the instruction that put the system into Power-down mode.
Note that If IDL bit and PD bit are set simultaneously, CPU will enter Power-down mode. Then it
does not go to Idle mode after exiting Power-down.
0
IDL
Idle mode
Setting this bit puts CPU into Idle mode. Under this mode, the CPU clock stops and Program
Counter (PC) suspends but all peripherals keep activated. After CPU is woken up from Idle, this bit
will be automatically cleared via hardware and the program continue executing the ISR of the very
interrupt source that woke the system up before. After return from the ISR, the device continues
execution at the instruction which follows the instruction that put the system into Idle mode.
