MS51
Dec. 17, 2019
Page
291
of 316
Rev 1.01
M
S51
SE
RIES
TE
CHNICA
L REF
ERE
N
CE MA
NU
A
L
Bit
Name
Description
2:0
PWMDIV[2:0]
PWM clock divider
This field decides the pre-scale of PWM clock source.
000 = 1/1.
001 = 1/2
010 = 1/4.
011 = 1/8.
100 = 1/16.
101 = 1/32.
110 = 1/64.
111 = 1/128.
CKCON
– Clock Control
Regiser
Address
Reset Value
CKCON
8EH, all pages
0000_0000b
7
6
5
4
3
2
1
0
FASTWK
PWMCKS
T1OE
T1M
T0M
T0OE
CLOEN
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
Bit
Name
Description
6
PWMCKS
PWM clock source select
0 = The clock source of PWM is the system clock FSYS.
1 = The clock source of PWM is the overflow of Timer 1.
PWMPL
– PWM Period Low Byte
Regiser
Address
Reset Value
PWMPL
D9H, all pages
0000_0000b
7
6
5
4
3
2
1
0
PWMP[7:0]
R/W
Bit
Name
Description
7:0
PWMnP[7:0]
PWMn period low byte
This byte with PWMnPH controls the period of the PWM generator signal.
PWMPH
– PWM Period High Byte
Regiser
Address
Reset Value
PWMPH
D1H, all pages
0000_0000b
7
6
5
4
3
2
1
0
PWMP[15:8]
