MS51
Dec. 17, 2019
Page
277
of 316
Rev 1.01
M
S51
SE
RIES
TE
CHNICA
L REF
ERE
N
CE MA
NU
A
L
I2STAT
– I
2
C Status
Regiser
Address
Reset Value
I2STAT
BDH, all pages
1111_1000 b
7
6
5
4
3
2
1
0
I2STAT[7:3]
0
0
0
R
R
R
R
Bit
Name
Description
7:3
I2STAT[7:3]
I
2
C status code
The MSB five bits of I2STAT contains the status code. There are 27 possible status codes.
When I2STAT is F8H, no relevant state information is available and SI flag keeps 0. All other 26
status codes correspond to the I
2
C states. When each of these status is entered, SI will be set
as logic 1 and a interrupt is requested.
2:0
0
Reserved
The least significant three bits of I2STAT are always read as 0.
I2DAT
– I
2
C Data
Regiser
Address
Reset Value
I2DAT
BCH, all pages
0000_0000 b
7
6
5
4
3
2
1
0
I2DAT[7:0]
R/W
Bit
Name
Description
7:0
I2DAT[7:0]
I
2
C data
I2DAT contains a byte of the I
2
C data to be transmitted or a byte, which has just received. Data
in I2DAT remains as long as SI is logic 1. The result of reading or writing I2DAT during I
2
C
transceiving progress is unpredicted.
While data in I2DAT is shifted out, data on the bus is simultaneously being shifted in to update
I2DAT. I2DAT always shows the last byte that presented on the I
2
C bus. Thus the event of lost
arbitration, the original value of I2DAT changes after the transaction.
I
2
C Data Shifting Direction.
I2CnDAT.7
I2CnDAT.6
I2CnDAT.5
I2CnDAT.4
I2CnDAT.3
I2CnDAT.2
I2CnDAT.1
I2CnDAT.0
I
2
C
Data Register:
shifting direction
I2ADDR
– I
2
C Own Slave Address