Nuvoton NuMicro MS51 Series, Техническое справочное руководство

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MS51
Dec. 17, 2019 Page 107 of 316 Rev 1.01
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T2MOD
– Timer 2 Mode
Regiser Address Reset Value
T2MOD C9H, all pages 0000_0000b
7 6 5 4 3 2 1 0
LDEN T2DIV[2:0] CAPCR CMPCR LDTS[1:0]
R/W R/W R/W R/W R/W
Bit Name Description
7 LDEN
Enable auto-reload
0 = Reloading RCMP2H and RCMP2L to TH2 and TL2 Disabled.
1 = Reloading RCMP2H and RCMP2L to TH2 and TL2 Enabled.
6:4 T2DIV[2:0]
Timer 2 clock divider
000 = Timer 2 clock divider is 1/1.
001 = Timer 2 clock divider is 1/4.
010 = Timer 2 clock divider is 1/16.
011 = Timer 2 clock divider is 1/32.
100 = Timer 2 clock divider is 1/64.
101 = Timer 2 clock divider is 1/128.
110 = Timer 2 clock divider is 1/256.
111 = Timer 2 clock divider is 1/512.
3 CAPCR
Capture auto-clear
This bit is valid only under Timer 2 auto-reload mode. It enables hardware auto-clearing TH2 and
TL2 counter registers after they have been transferred in to RCMP2H and RCMP2L while a
capture event occurs.
0 = Timer 2 continues counting when a capture event occurs.
1 = Timer 2 value is auto-cleared as 0000H when a capture event occurs.
2 CMPCR
Compare match auto-clear
This bit is valid only under Timer 2 compare mode. It enables hardware auto-clearing TH2 and
TL2 counter registers after a compare match occurs.
0 = Timer 2 continues counting when a compare match occurs.
1 = Timer 2 value is auto-cleared as 0000H when a compare match occurs.
1:0 LDTS[1:0]
Auto-reload trigger select
These bits select the reload trigger event.
00 = Reload when Timer 2 overflows.
01 = Reload when input capture 0 event occurs.
10 = Reload when input capture 1 event occurs.
11 = Reload when input capture 2 event occurs.