MS51
Dec. 17, 2019
Page
195
of 316
Rev 1.01
M
S51
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RIES
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CHNICA
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CE MA
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Open-Drain Mode
6.4.1.4
The open-drain mode turns off all pull-high transistors and only drives the pull-low of the port pin when
the port latch is given by logic 0. If the port latch is logic 1, it behaves as if in input-only mode. To be
used as an output pin generally as I
2
C lines, an open-drain pin should add an external pull-high,
typically a resistor tied to V
DD
. User needs to take care that an open-drain pin with its port latch as
logic 1 should be given with a determined voltage level by external devices or resistors. A floating pin
will induce leakage current especially in Power-down mode.
Port Pin
Input
Port Latch
N
Figure 6.4-4 Open-Drain Mode Structure
6.4.2
Control Registers of GPIO
The MS51 has a lot of I/O control registers to provide flexibility in all kinds of applications. The SFR
related with I/O ports can be categorized into four groups: input and output control, output mode
control, input type and sink current control, and output slew rate control. All of SFR are listed as
follows.
Input and Output Data Control
6.4.2.1
These registers are I/O input and output data buffers. Reading gets the I/O input data. Writing forces
the data output. All of these registers are bit-addressable.
Pn
– Port n (Bit-addressable)
Regiser
Address
Reset Value
P0
80H, all pages, bit addressable
1111_1111 b
P1
90H, all pages, bit addressable
1111_1111 b
P2
A0H, all pages, bit addressable
0000_0001 b
P3
B0H, all pages, bit addressable
0000_0001 b
7
6
5
4
3
2
1
0
Pn.7
Pn.6
Pn.5
Pn.4
Pn.3
Pn.2
Pn.1
Pn.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P0 / P1
Bit
Name
Description
7:0
P0[7:0]
Port 0
Port 0 is an maximum 8-bit general purpose I/O port.
P2
Bit
Name
Description