6-6 Troubleshooting and Repair
Explanation of test terms for beep code table
The following terms are used in the Test Performed column of the beep code
table:
1.
Pattern test - One or more particular patterns are written to a location then
read back from the same location. Examples of patterns used are 55h and
AAh. If the value read does not match the value written, the test is
considered a failure.
2.
Rolling ones test - Several patterns are constructed. These patterns represent
a one rolling through the given location. For example, to roll a one through
three bits, the following patterns would be constructed: 001, 010, 011, 100,
101, 110, and 111. The patterns are written to the location and then read
back, one by one. If the value read does not match the value written, the test
is considered a failure.
3.
Rolling zeros test - Several patterns are constructed. These patterns
represent a zero rolling through the given location. For example, to roll a
zero through three bits, the following patterns would be constructed: 011,
001, and 000. The patterns are written to the location and then read back,
one by one. If the value read does not match the value written, the test is
considered a failure.
4.
Checksum test - All of the values in a given range of locations are added
together. The range includes a location which when added to sum of the
ranges, will produce a known result, such as zero.
Beep codes for system board errors
BIOS Beep Codes
Beep
Code
Diagnostic
Code
Description
Test Performed
None
01h
CPU registers test in
progress or failure
Pattern test of most of the 16-bit CPU registers.
Failure will result in a system halt.
1-1-3
02h
CMOS write/read test in
progress or failure.
Rolling ones test in the shutdown byte (offset
0Eh) of the CMOS RAM. Failure will result in a
system halt.
1-1-4
03h
ROM BIOS checksum test in
progress or failure.
The range of ROM that includes the BIOS is
checksummed. Failure will result in a system
halt.
1-2-1
04h
Programmable interval timer
0 test in progress or failure.
Over a period of time, the current count values
in timer 0 are read and accumulated by ORing
them into the values read so far. It is expected
that during the time period, all bits will be set.
Failure will result in a system halt.
1-2-2
05h
DMA channel 0 address and
count register test in progress
or failure.
Rolling ones and rolling zeros test of the
address and count registers of DMA channel 0.
Failure will result in a system halt.
1-2-3
06h
DMA page register write/read
test in progress of failure.
Pattern test of DMA page registers. Failure will
result in a system halt.
