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CHAPTER 8 WATCH TIMER
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User’s Manual U11302EJ4V0UM
8.2 Watch Timer Configuration
The watch timer consists of the following hardware.
Table 8-2. Watch Timer Configuration
Item
Configuration
Counter
5 bits x 1
Control registers
Timer clock select register 2 (TCL2)
Watch timer mode control register (TMC2)
8.3 Watch Timer Control Registers
The following two registers are used to control the watch timer.
•
Timer clock select register 2 (TCL2)
•
Watch timer mode control register (TMC2)
(1) Timer clock select register 2 (TCL2)
(See
Figure 8-2
)
This register sets the watch timer count clock.
TCL2 is set with an 8-bit memory manipulation instruction.
RESET input sets TCL2 to 00H.
Remark
Besides setting the watch timer count clock, TCL2 sets the watchdog timer count clock and
buzzer output frequency.
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