CHAPTER 5 CLOCK GENERATOR
118
User’s Manual U11302EJ4V0UM
5.6.2 System clock and CPU clock switching procedure
This section describes the procedure for switching between the system clock and CPU clock.
Figure 5-10. System Clock and CPU Clock Switching
[1] The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released
by setting the RESET signal to high level, the main system clock starts oscillating. At this time, the oscillation
stabilization time (2
17
/f
X
) is secured automatically.
After that, the CPU starts executing the instruction at the minimum speed of the main system clock (6.4
µ
s when
operated at 5.0 MHz).
[2] After the lapse of a sufficient time for the V
DD
voltage to increase to enable operation at maximum speeds, the
processor clock control register (PCC) is rewritten and the maximum-speed operation is carried out.
[3] Upon detection of a decrease of the V
DD
voltage due to an interrupt request signal, the main system clock is
switched to the subsystem clock (which must be in an oscillation stable state).
[4] Upon detection of V
DD
voltage reset due to an interrupt request signal, bit 7 (MCC) of PCC is set to 0 and
oscillation of the main system clock is started. After the lapse of time required for stabilization of oscillation,
PCC is rewritten and the maximum-speed operation is resumed.
Caution When the main system clock is stopped and the subsystem clock is operating, switch to the
main system clock after securing the oscillation stabilization time by program.
Wait (26.2 ms: @5.0 MHz)
Internal reset operation
System clock
CPU clock
Interrupt
request
signal
Minimum
speed
operation
Maximum speed
operation
f
X
f
X
f
XT
Subsystem clock
operation
f
X
High-speed
operation
RESET
V
DD
Содержание mPD780208 Subseries
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