CHAPTER 20 INSTRUCTION SET
386
User’s Manual U11302EJ4V0UM
20.2 Operation List
Instruc- Mnemonic
Operands
Bytes
Operation
tion
Group
MOV
r, #byte
2
4
–
r
←
byte
saddr, #byte
3
6
7
(saddr)
←
byte
sfr, #byte
3
–
7
sfr
←
byte
A, r
Note 3
1
2
–
A
←
r
r, A
Note 3
1
2
–
r
←
A
A, saddr
2
4
5
A
←
(saddr)
saddr, A
2
4
5
(saddr)
←
A
A, sfr
2
–
5
A
←
sfr
sfr, A
2
–
5
sfr
←
A
A, !addr16
3
8
9
A
←
(addr16)
!addr16, A
3
8
9
(addr16)
←
A
PSW, #byte
3
–
7
PSW
←
byte
×
×
×
A, PSW
2
–
5
A
←
PSW
PSW, A
2
–
5
PSW
←
A
×
×
×
A, [DE]
1
4
5
A
←
(DE)
[DE], A
1
4
5
(DE)
←
A
A, [HL]
1
4
5
A
←
(HL)
[HL], A
1
4
5
(HL)
←
A
A, [HL+byte]
2
8
9
A
←
(HL+byte)
[HL+byte], A
2
8
9
(HL+byte)
←
A
A, [HL+B]
1
6
7
A
←
(HL+B)
[HL+B], A
1
6
7
(HL+B)
←
A
A, [HL+C]
1
6
7
A
←
(HL+C)
[HL+C], A
1
6
7
(HL+C)
←
A
XCH
A, r
Note 3
1
2
–
A
↔
r
A, saddr
2
4
6
A
↔
(saddr)
A, sfr
2
–
6
A
↔
sfr
A, !addr16
3
8
10
A
↔
(addr16)
A, [DE]
1
4
6
A
↔
(DE)
A, [HL]
1
4
6
A
↔
(HL)
A, [HL+byte]
2
8
10
A
↔
(HL+byte)
A, [HL+B]
2
8
10
A
↔
(HL+B)
A, [HL+C]
2
8
10
A
↔
(HL+C)
Notes 1.
When the internal high-speed RAM area is accessed or an instruction with no data access.
2.
When an area except the internal high-speed RAM area is accessed.
3.
Except r = A
Remark
One instruction clock cycle is one cycle of the CPU clock (f
CPU
) selected by the processor clock control
register (PCC).
Z
AC CY
Note 2
Note 1
Clocks
Flag
8-bit
data
transfer
Содержание mPD780208 Subseries
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