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Preliminary User’s Manual U15839EE1V0UM00
List of Figures
Memory Map (µPD703129 (A), µPD703129 (A1))....................................................... 69
Peripheral Command Register (PHCMD) Format ..................................................... 105
Internal peripheral function wait control register (VSWC) Format ............................. 107
SRAM, External ROM, External I/O Access Timing (1/6).......................................... 139
On-Page/Off-Page Judgment during Page ROM Connection (1/2)........................... 147
Configuration of 4 KB 2-Way Set-Associative Instruction Cache .............................. 157
DMA Source Address Registers DSAH0 to DSAH3 (DSAH0 to DSAH3) ................. 170
DMA Source Address Registers DSAL0 to DSAL3 (DSAL0 to DSAL3).................... 171
DMA Destination Address Registers 0H to 3H (DDA0H to DDA3H) ......................... 172
DMA Destination Address Registers L0 to L3 (DDAL0 to DDAL3)............................ 173
DMA Transfer Count Registers 0 to 3 (DBC0 to DBC3)............................................ 174
DMA Addressing Control Registers 0 to 3 (DADC0 to DADC3) (1/2)........................ 175
DMA Channel Control Registers 0 to 3 (DCHC0 to DCHC3) .................................... 177
Содержание mPD703128
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