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Chapter 10
Timer
Preliminary User’s Manual U15839EE1V0UM00
10.3.4 Control
registers
(1)
Timer Gn Mode Register (TMGMn) (n = 0, 1)
This register can be read/written in 16-bit, 8-bit or 1-bit units.
Figure 10-30:
Timer Gn Mode Register (TMGMn) (1/2)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Address
Initial
value
TMGM0 POWER OLDE CSE12 CSE11 CSE10 CSE02 CSE01 CSE00 CCSG5 CCSG0
0
0
CLRG1 TMG1E CLRG0 TMG0E FFFF F640H
0000H
TMGM1 POWER OLDE CSE12 CSE11 CSE10 CSE02 CSE01 CSE00 CCSG5 CCSG0
0
0
CLRG1 TMG1E CLRG0 TMG0E FFFF F680H
0000H
Bit Position
Bit Name
Function
15
POWER
Timer Gn Operation control.
0: operation Stop
the capture registers and TMGSTn register are cleared
the TOGnm pins (m = 1 to 4) are inactive all the time
1: operation enable
Remark:
At least 7 peripheral-clocks (f
PCLK
) are need to start the timer function
14
OLDE
Set Output Delay Operation.
0: Don’t perform output delay operation
1: Set output delay to n count-clocks
Caution:
When the POWER-Bit is set, the rewriting of this Bit is
prohibited! Simultaneously writing with the POWER bit is allowed.
Remark:
The delay operation is used for EMI counter measures.
13 to 8
CSEx2,
CSEx1,
CSEx0
Selects internal count clock of TMG
CSEx2
CSEx1
CSEx0
Count
Clock
0
0
0
f
PCLK
0
0
1
f
PCLK
/2
0
1
0
f
PCLK
/4
0
1
1
f
PCLK
/8
1
0
0
f
PCLK
/16
1
0
1
f
PCLK
/32
1
1
0
f
PCLK
/64
1
1
1
f
PCLK
/128
Caution:
When the POWER-Bit is set, the rewriting of this Bits are
prohibited! Simultaneously writing with the POWER bit is allowed.
Remarks: 1. x = 0, 1
2. f
PCLK
: peripheral clock
Содержание mPD703128
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