Chapter 4
Register Descriptions
© National Instruments Corporation
4-75
VME-MXI-2 User Manual
DMA Destination Address Register (DARx)
DAR1 VMEbus A24 or A32 Offset:
D18 (hex)
DAR2 VMEbus A24 or A32 Offset:
E18 (hex)
Attributes:
Read/Write
32, 16, 8-bit accessible
31
30
29
28
27
26
25
24
DA[31]
DA[30]
DA[29]
DA[28]
DA[27]
DA[26]
DA[25]
DA[24]
23
22
21
20
19
18
17
16
DA[23]
DA[22]
DA[21]
DA[20]
DA[19]
DA[18]
DA[17]
DA[16]
15
14
13
12
11
10
9
8
DA[15]
DA[14]
DA[13]
DA[12]
DA[11]
DA[10]
DA[9]
DA[8]
7
6
5
4
3
2
1
0
DA[7]
DA[6]
DA[5]
DA[4]
DA[3]
DA[2]
DA[1]
DA[0]
This register stores the base address to be used for the destination.
Bit
Mnemonic
Description
31-0
DA[31:0]
Destination Address
These bits store the address used to access the
destination. The value of these bits is modified
after each successful data transfer to the
destination during the DMA operation, according
to the ASCEND bit in the DMA Destination
Configuration Register (DCRx). If the initial
value of these bits is not aligned to the transfer
size indicated by the TSIZE[1:0] bits in the
DCRx, the DMA controller performs smaller
transfers until address alignment occurs.
However, if 64-bit data transfers are used for the
destination, this register must be programmed
with an address divisible by 8. In the case that
the DMA controller terminates due to an error
with the destination transfers, these bits would
indicate the address that caused the error. When
the destination is DRAM onboard the
VME-MXI-2, these bits must be programmed
with the offset of the destination location within
the VME-MXI-2 module’s address space, not the
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