Chapter 4
Register Descriptions
© National Instruments Corporation
4-69
VME-MXI-2 User Manual
9-8
TSIZE[1:0]
Transfer Size
These bits control the transfer size to be used to
access the source. Write these bits with 01
(binary) to perform 8-bit transfers, 10 (binary) to
perform 16-bit transfers, and 11 (binary) to
perform 32-bit or 64-bit transfers. The DMA
controller can distinguish between 32-bit and
64-bit transfers using the AM[5:0] bits. These
bits are cleared by a hard reset and are not
affected by a soft reset.
7-6
PORT[1:0]
Port
These bits control the bus on which the source is
located. Write these bits with 01 (binary) if the
source is DRAM onboard the VME-MXI-2,
10 (binary) if the source is on the VMEbus, and
11 (binary) if the source is on the MXIbus. These
bits are cleared by a hard reset and are not
affected by a soft reset.
5-0
AM[5:0]
Address Modifiers
These bits provide the address modifier code
used to access the source. Even when the source
is on the MXIbus, the VMEbus equivalent
address modifier code should be written to these
bits (the MXIbus address modifier code should
not be written to these bits, because the DMA
controller converts VMEbus address modifier
codes when the source is on the MXIbus).
Table F-1, Address Modifier Codes, in
Appendix F, DMA Programming Examples,
describes the address modifier codes that can be
written to these bits. When the source is DRAM
onboard the VME-MXI-2, these bits must be
written with 0. These bits are cleared by a hard
reset and are not affected by a soft reset.
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