Chapter 4
Register Descriptions
VME-MXI-2 User Manual
4-60
© National Instruments Corporation
DMA Channel Operation Register (CHORx)
CHOR1 VMEbus A24 or A32 Offset:
D00 (hex)
CHOR2 VMEbus A24 or A32 Offset:
E00 (hex)
Attributes:
Read/Write
32, 16, 8-bit accessible
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
CLRDONE
0
0
FRESET
ABORT
STOP
0
START
This register is used to control overall operation of the DMA controller, such as starting a
transfer after all the other DMA registers have been programmed.
Bit
Mnemonic
Description
31-8
0
Reserved
These bits are reserved. Write each of these bits
with 0 when writing the CHORx. The value
these bits return when read is meaningless.
7
CLRDONE
Clear DONE
This bit can be written with a 1 to clear the
DONE bit in the DMA Channel Status Register
(CHSRx). The DONE bit also clears
automatically when a new DMA operation is
started. It is not necessary to clear the
CLRDONE bit after writing a 1 to it.
6-5
0
Reserved
These bits are reserved. Write each of these bits
with 0 when writing the CHORx. The value
these bits return when read is meaningless.
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