Chapter 4
Register Descriptions
VME-MXI-2 User Manual
4-56
© National Instruments Corporation
Shared MXIbus Status/Control Register (SMSR/SMCR)
VMEbus A24 or A32 Offset:
C40 (hex)
Attributes:
Read/Write
32, 16, 8-bit accessible
31
30
29
28
27
26
25
24
0
0
DMA2MBS
DMA1MBS
DMAMB S/N*
0
0
0
23
22
21
20
19
18
17
16
1
1
FAIR
0
0
PAREN
0
1
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
1
7
6
5
4
3
2
1
0
0
0
0
0
MBTO[3]
MBTO[2]
MBTO[1]
MBTO[0]
This register provides control bits for the configurable features of the MXIbus interface
on the VME-MXI-2.
Bit
Mnemonic
Description
31-30
0
Reserved
These bits are reserved. Write these bits with 0
when writing to the SMCR.
29
DMA2MBS
DMA Controller 2 MXIbus Block Select
This bit, combined with the DMAMB S/N* bit,
controls whether block cycles to the MXIbus
from DMA Controller 2 are performed as normal
MXIbus block cycles or synchronous MXIbus
burst cycles. Non-block cycles to the MXIbus
are unaffected by this bit. Write a 1 to both
DMA2MBS and DMAMB S/N* to cause DMA
Controller 2 block cycles to the MXIbus to be
synchronous burst cycles. Write a 1 to
DMA2MBS and a 0 to DMAMB S/N* to cause
DMA Controller 2 block cycles to the MXIbus to
be normal block cycles. When DMA2MBS is
written with a 0 the bit is unaffected (it remains
in whatever state it was in before the write). This
bit returns 1 when read if synchronous burst
cycles are enabled and 0 when normal block
cycles are enabled.
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