© National Instruments
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cDAQ-9185/9189 User Manual
Buffered (Sample Clock) Edge Counting
With buffered edge counting (edge counting using a sample clock), the counter counts the
number of edges on the Source input after the counter is armed. The value of the counter is
sampled on each active edge of a sample clock and stored in the FIFO. The STC3 transfers the
sampled values to host memory using a high-speed data stream.
The count values returned are the cumulative counts since the counter armed event. That is, the
sample clock does not reset the counter. You can configure the counter to sample on the rising
or falling edge of the sample clock.
Figure 6-4 shows an example of buffered edge counting. Notice that counting begins when the
counter is armed, which occurs before the first active edge on Sample Clock.
Figure 6-4.
Buffered (Sample Clock) Edge Counting
Controlling the Direction of Counting
In edge counting applications, the counter can count up or down. You can configure the counter
to do the following:
•
Always count up
•
Always count down
•
Count up when the Counter 0 B input is high; count down when it is low
For information about connecting counter signals, refer to the
Default Counter/Timer Routing
section.
3
6
3
Co
u
nter Armed
S
OURCE
Sa
mple Clock
(
Sa
mple on Ri
s
ing Edge)
Co
u
nter V
a
l
u
e
B
u
ffer
1
0
7
6
3
4
5
2
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