M68360QUADS-040 Hardware User’s Manual
SUPPORT INFORMATION
58
FIGURE B-3 M68360QUADS-040 Write Cycle to Host
B.3.3
M68360QUADS-040 Interrupt to the Host
The M68360QUADS-040 can generate an interrupt to the Host. The interrupt request and acknowledge
sequence is shown in FIGURE B-4.
The sequence is as follows:
1.
The M68360QUADS-040 places a service request code on the parallel port data bus
(buffer disabled) and asserts the ADS_INT and the HOST_BRK~ signals. The
HOST_BRK~ signal is an open-collector signal, asserted low, common to all
M68360QUADS-040 boards which will appear immediately on the port. The ADS_INT
signal will not appear on the port until the board is selected by the Host.
2.
The Host detects the HOST_BRK~ signal and polls each M68360QUADS-040 address to
determine the interrupting board.
3.
The Host asserts the HST_ACK signal, enabling the data buffer in the M68360QUADS-
040.
4.
The Host reads the service request code on the data bus.
5.
The Host negates the HST_ACK signal.
6.
The Host asserts the INT_ACK signal, which resets the HOST_BRK latch in the
M68360QUADS-040 and negates the HOST_BRK~ signal. the HOST_BRK~ signal can
still be low (asserted) if another M68360QUADS-040 board is driving it low.
7.
The selected M68360QUADS-040 detects the INT_ACK signal and negates the ADS_INT
signal.
8.
The Host negates the INT_ACK signal and ends the cycle.
ADS_SEL(0:2)
HST_ACK
PD(0:7)
ADDRESS VALID
1
2
3
4
5
DATA VALID
ADS_REQ
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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