M68360QUADS-040 Hardware User’s Manual
FUNCTIONAL DESCRIPTION
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4 - FUNCTIONAL DESCRIPTION
4.1
INTRODUCTION
This chapter details the hardware design of the M68360QUADS-040, and describes each module in order
to simplify the design.
4.2
Master MC68EC040
The CPU on the M68360QUADS-040 is a 33 MHz MC68EC040, running at 25 MHz, which uses the slave
QUICC’s “68EC040 companion mode” as the memory controller, the interrupt controller, bus arbiter and
other system functions usually provided by dedicated logic or peripherals. Due to this “companion” mode
support, the MC68EC040 interfaces gluelessly to the QUICC, while some of the QUICC pins change their
function to match these of the 68EC040.
The MC68EC040 is unbuffered from the slave QUICC and the other peripherals (except for the externally
multiplexed DRAM address lines). In order to demonstrate the “glueless” concept under practical test and
evaluation.
Address lines A(28:31) of the slave QUICC are used in their alternate function as WE(0:3)~ to avoid having
to generate them externally. As a result only 256 MByte of memory may be accessed by both the 68EC040
and the QUICC with chip-select support.
All the pins of the MC68EC040 device are available unbuffered to the user through the logic analyzer
connectors. The user can monitor the 040 activity during its development stage.
4.2.1
RESET for the 68EC040 & the QUICC
There are four basic types of reset, regarding their source and consequence, available on the
M68360QUADS-040 board:
1.
QUICC Generated Reset - These types of reset are generated internally by the QUICC and
include: Power-up & Software Watch-Dog. Double-Bus-Fault reset is not supported when
the QUICC is in EC040 companion mode.
2.
SOFT Reset - may be caused by either depressing the SOFT-RESET push-button or when
the ADI-port’s soft-reset signal is asserted by the remote host. When either happens, the
040 is reset while the QUICC is soft-reset, i.e., the configuration of the QUICC is
unchanged, preserving the contents of the DRAM.
3.
HARD-RESET - may be generated by either depressing SOFT-RESET in conjunction with
the ABORT push-button or when the ADI-port’s hard-reset signal is asserted by the remote
host. When either happens, the 040 is reset and the QUICC is hard-reset, i.e., all the
QUICC’s sub-modules are reset, including configuration and clock logic.
4.
RESET Instruction - When the RESET instruction is executed by the MC68EC040,
RESETS* line is asserted to the QUICC, which in turn, asserts this line to complete 512
clock cycles. Execution of RESET instruction does not cause the reset of the MC68EC040
itself, therefore not interrupting the software flow.
1
1. It was observed that the EC040 may start the next bus cycle faster than the QUICC can recover from the reset; there-
fore, it is recommended that the RESET instruction is loaded to an even cache-line address and executed from the
cache.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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