M68360QUADS-040 Hardware User’s Manual
OPERATING INSTRUCTIONS
24
3.4.13
Base Register 5 and Option Register 5
Base register 5 (BR5) and Option register 5 (OR5) control the operation of CS5~ pin of the slave QUICC,
which is connected to the Status Register and to the level -7 interrupt logic. When CS5~ is asserted (for
read-only) both the Status Register is read and all existing level - 7 status bits are cleared.
BR5 must be initialized to ’01230003’, and OR5 must be initialized to ’0FFFF800’ to obtain the memory
map as described in TABLE 3-2.
3.4.14
Base Register 6 and Option Register 6
Since CS6~ is not being used on the M68360QUADS-040, BR6 and OR6 are not initialized by the
debugger. CS6~ is available for user’s applications via the expansion connector - P11.
3.4.15
Base Register 7 and Option Register 7
Since CS7~ is not being used on the M68360QUADS-040, BR7 and OR7 are not initialized by the
debugger. CS7~ is available for user’s applications via the expansion connector - P11.
3.4.16
Port A Open Drain Register
Port A of the slave QUICC is 16 pins port, and each pin may be configured as general purpose I/O pin or
as dedicated peripheral interface pin. The port A open drain register (PAODR) configures the drivers of port
A pins as open-drain or as active drivers. The PAODR must be initialized to ’0000’ to select the active
drivers configuration.
3.4.17
Port A Data Register
The Port A data register (PADAT) can be read to check the data at the pin. If a port pin is configured as
general purpose output pin, the value in the PADAT for that pin is driven onto the pin.
On the M68360QUADS-040, port A is used for serial channels as well as for ADI parallel port. PADAT must
be initialized to ’3F00’ before configuring the other port registers.
3.4.18
Port A Data Direction Register
The port A data direction register (PADIR) has different functions according to the configuration of the port
pins. If a pin is a general purpose I/O pin, the value in the PADIR for that pin defines the direction of the
pin. If a pin is a dedicated peripheral interface pin, the value in the PADIR for that pin may select one of
two dedicated functions of the pin. PADIR must be initialized to ’F000’.
3.4.19
Port A Pin Assignment Register
The port A pin assignment register (PAPAR) configures the function of the port pins. If the value in the
PAPAR for a pin is ’0’, the pin is general purpose I/O, otherwise the pin is a dedicated peripheral interface
pin. The PAPAR must be initialized to ’0F3F’.
3.4.20
Port B Open Drain Register
Port B of the slave QUICC is a 18 bit port, and each pin may be configured as general purpose I/O pin or
as dedicated peripheral interface pin. The port B open drain register (PBODR) configures the drivers of port
B pins as open-drain or as active drivers. The PBODR must be initialized to ’0000’ to select the active
drivers configuration.
3.4.21
Port B Data Register
Port B data register (PBDAT) can be read to check the data at the pin. If a port pin is configured as general
purpose output pin, the value in the PBDAT for that pin is driven onto the pin. It is recommended to initialize
PBDAT to ’3FFFF’ before configuring the other port registers.
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