2-18
AC Timings
Figure 2-12 shows Host DMA read timing.
Figure 2-13 shows Host DMA write timing.
Figure 2-12. Host DMA Read Timing Diagram
Figure 2-13. Host DMA Write Timing Diagram
RX[0–3]
Read
Data
Valid
64
44a
63
44b
51
50
49
52
(Output)
HREQ
HACK or
HWR, HDS,
HRD (Input)
HD[0–15]
(Output)
TX[0–3]
Write
Data
Valid
63
64
46
45
47
48
(Output)
HREQ
HACK or
HWR, HDS,
HRD (Input)
HD[0–15]
(Output)