2-15
AC Timings
Figure 2-8 and Figure 2-9 show HDI16 read signal timing. Figure 2-10 and Figure 2-11 show HDI16
write signal timing.
47
Host data input setup time before write data strobe
deassertion
8
Host data input setup time before HACK write deassertion
—
3.3
—
ns
48
Host data input hold time after write data strobe
deassertion
8
Host data input hold time after HACK write deassertion
—
3.3
—
ns
49
Read data strobe assertion to output data active from high
impedance
4
HACK read assertion to output data active from high
impedance
—
3.3
—
ns
50
Read data strobe assertion to output data valid
4
HACK read assertion to output data valid
(1.5
×
T
C
) + 3.3
—
8.25
ns
51
Read data strobe deassertion to output data high
impedance
4
HACK read deassertion to output data high impedance
—
—
3.3
ns
52
Output data hold time after read data strobe deassertion
4
Output data hold time after HACK read deassertion
—
3.3
—
ns
53
HCS[1–2] assertion to read data strobe assertion
4
—
3.3
—
ns
54
HCS[1–2] assertion to write data strobe assertion
8
—
3.3
—
ns
55
HCS[1–2] assertion to output data valid
T
C
+ 3.3
—
6.6
ns
56
HCS[1–2] hold time after data strobe deassertion
9
—
0.0
—
ns
57
HA[0–3], HRW setup time before data strobe assertion
9
•
Read
•
Write
—
0
3.3
—
—
ns
ns
58
HA[0–3], HRW hold time after data strobe deassertion
9
—
3.3
—
ns
61
Delay from read data strobe deassertion to host request
deassertion for “Last Data Register” read
4, 5, 10
(2.5
×
T
C
)
+ 3.3
—
11.6
ns
62
Delay from write data strobe deassertion to host request
deassertion for “Last Data Register” write
5,8,10
(2.5
×
T
C
)
+ 3.3
—
11.6
ns
63
Delay from DMA HACK (OAD=0) or Read/Write data
strobe(OAD=1) deassertion to HREQ assertion.
(2.5
×
T
C
) + 3.3
11.6
ns
64
Delay from DMA HACK (OAD=0) or Read/Write data
strobe(OAD=1) assertion to HREQ deassertion
(3.5
×
T
C
)
+ 3.3
—
14.9
ns
Notes:
1.
T
C
= 1/ DSPCLK. At 300 MHz, T
C
= 3.3 ns
2.
In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is
programmable.
3.
V
CC
= 3.3 V ± 0.3 V; T
J
=
–40°C to +100 °C, C
L
= 50 pF
4.
The read data strobe is HRD/HRD in the dual data strobe mode and HDS/HDS in the single data
strobe mode.
5.
In 64-bit mode, The “last data register” is the register at address $7, which is the last location to be
read or written in data transfers. This is RX0/TX0 in the little endian mode (HBE = 0), or RX3/TX3 in
the big endian mode (HBE = 1).
6.
This timing is applicable only if a read from the “last data register” is followed by a read from the RXL,
RXM, or RXH registers without first polling RXDF or HREQ bits, or waiting for the assertion of the
HREQ/HREQ signal.
7.
This timing is applicable only if two consecutive reads from one of these registers are executed.
8.
The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.
9.
The data strobe is host read (HRD/HRD) or host write (HWR/HWR) in the dual data strobe mode and
host data strobe (HDS/HDS) in the single data strobe mode.
10. The host request is HREQ/HREQ in the single host request mode and HRRQ/HRRQ and
HTRQ/HTRQ in the double host request mode. HRRQ/HRRQ is deasserted only when HOTX fifo is
empty, HTRQ/HTRQ is deasserted only if HORX fifo is full (treat as level Host Request).
Table 2-18. Host Interface (HDI16) Timing
1, 2
(Continued)
Number
Characteristics
3
Expression
Min
Max
Unit
