Motorola Digital DNA MSC8101, Технические данные инструкция

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2-14
AC Timings
2.7.3.2 DMA Data Transfers
Table 2-17 describes the DMA signal timing.
The DREQ signal is synchronized with the falling edge of REFCLK . DONE timing is relative to the rising
edge of
REFCLK
. To achieve fast response, a synchronized peripheral should assert
DREQ
according to
the timings in Table 2-17. Figure 2-7 shows synchronous peripheral interaction.
2.7.4 HDI16 Signals
Table 2-17. DMA Signals
Number Characteristic Minimum Maximum Units
72 DREQ setup time before REFCLK falling edge 6 — ns
73 DREQ hold time after REFCLK falling edge 0.5 — ns
74 DONE setup time before REFCLK rising edge 9 — ns
75 DONE hold time after REFCLK rising edge 0.5 — ns
76 DACK/DRACK/DONE delay after REFCLK rising edge 0.5 9 ns
Figure 2-7. DMA Signals
Table 2-18. Host Interface (HDI16) Timing
1, 2
Number Characteristics
3
Expression Min Max Unit
44a Read data strobe assertion width
4
HACK read assertion width
T
C
+ 3.3 6.6 — ns
44b Read data strobe deassertion width
4
HACK read deassertion width
T
C
+ 3.3 6.6 — ns
44c Read data strobe deassertion width
4
after “Last Data
Register” reads
5,6
, or between two consecutive CVR, ICR,
or ISR reads
7
HACK deassertion width after “Last Data Register” reads
5,6
(2.5
×
T
C
) + 3.3 11.6 — ns
45 Write data strobe assertion width
8
HACK write assertion width
T
C
+ 3.3 6.6 — ns
46 Write data strobe deassertion width
8
HACK write deassertion width after ICR, CVR and Data
Register writes
5
(2.5
×
T
C
) + 3.3 11.6 — ns
REFCLK
DREQ
DONE Input
DACK/DONE/DRACK Outputs
73
72
74
75
76