Figure 3-18. SAMA7G5 PIOD Bank Distribution
PIOD Distribution
EXT40_GPIO_PD31
DBGU_TX_PD16
DBGU_RX_PD17
SDMMC2_WILC3000_RSTN_PD2
SDMMC2_WILC3000_CMD_PD3
SDMMC2_WILC3000_CK_PD4
SDMMC2_WILC3000_DAT0_PD5
SDMMC2_WILC3000_DAT1_PD6
SDMMC2_WILC3000_DAT2_PD7
SDMMC2_WILC3000_DAT3_PD8
MCP16502_INT_PD9
USBA_VBUSDETECT_PD11
WILC3000_INT_PD10
MIKROBUS1_TX_PD18
MIKROBUS1_RX_PD19
MIKROBUS1_AN_PD0
MIKROBUS2_AN_PD1
CANTX0_PD12
CANRX0_PD13
CANTX1_PD14
CANRX1_PD15
PD0 G3
PD1 F4
PD2 H12
PD3 B15
PD4 A15
PD5 A16
PD6 G12
PD7 J11
PD8 B13
PD9 D19
PD10 M12
PD11 A20
PD12 P12
PD13 H18
PD14 C19
PD15 R12
PD16 D18
PD17 G18
PD18 B19
PD19 N11
PD20 C18
PD21 F18
PD22 A19
PD23 K12
PD24 D17
PD25 K10
PD26 G14
PD27 D16
PD28 J12
PD29 B18
PD30 H13
PD31 C16
SAMA7G54
U4D
PD22
PD23
PD24
PD20
PD21
PD25
PD26
PD27
PD28
PD29
PD30
The following table describes each PIOD bank function.
Table 3-8. SAMA7G5 PIOs Pin Assignment and Signal Description
PIO
Power Rail
Function
Signal Description
PD0
VDDIN33
AD14
mikroBUS 1 analog input
PD1
VDDIN33
AD15
mikroBUS 2 analog input
PD2
VDDSDMMC2
SDMMC2_RSTN
WILC3000 SDIO reset line
PD3
VDDSDMMC2
SDMMC2_CMD
WILC3000 SDIO command line
PD4
VDDSDMMC2
SDMMC2_CK
WILC3000 SDIO clock line
PD5
VDDSDMMC2
SDMMC2_DAT0
WILC3000 SDIO data line 0
PD6
VDDSDMMC2
SDMMC2_DAT1
WILC3000 SDIO data line 1
PD7
VDDSDMMC2
SDMMC2_DAT2
WILC3000 SDIO data line 2
PD8
VDDSDMMC2
SDMMC2_DAT3
WILC3000 SDIO data line 3
PD9
VDDIOP1
PD9
MCP16502 interrupt
PD10 VDDIOP1
PD10
WILC3000 interrupt
PD11 VDDIOP1
PD11
Power detect USB port A
PD12 VDDIOP1
CANTX0
CAN transmit line 0
PD13 VDDIOP1
CANRX0
CAN receive line 0
PD14 VDDIOP1
CANTX1
CAN transmit line 1
PD15 VDDIOP1
CANRX1
CAN receive line 1
SAMA7G54-EK
Function Blocks
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2022 Microchip Technology Inc.
and its subsidiaries
User Guide
DS50003273A-page 28