...........continued
PIO
Power Rail
Function
Signal Description
PA15
VDDIOP0
G0_TXEN
Transmit enable
PA16
VDDIOP0
G0_TX0
Transmit data line 0
PA17
VDDIOP0
G0_TX1
Transmit data line 1
PA18
VDDIOP0
G0_RXCTL
Receive data valid and receive error
PA19
VDDIOP0
G0_RX0
Receive data line 0
PA20
VDDIOP0
G0_RX1
Receive data line 1
PA21
VDDIOP0
PA21
Ethernet 1 interrupt (10/100 Ethernet)
PA22
VDDIOP0
G0_MDC
Management data clock
PA23
VDDIOP0
G0_MDIO
Management data input/output
PA24
VDDIOP0
G0_TXCK
Transmit clock
PA25
VDDIOP0
G0_125CK
125 MHz clock
PA26
VDDIOP0
G0_TX2
Transmit data line 2
PA27
VDDIOP0
G0_TX3
Transmit data line 3
PA28
VDDIOP0
G0_RX2
Receive data line 2
PA29
VDDIOP0
G0_RX3
Receive data line 3
PA30
VDDIOP0
G0_RXCK
Receive clock
PA31
VDDIOP0
PA31
Ethernet 0 interrupt (Gigabit Ethernet)
3.2.5.2
PIOB Bank
The PIOB bank is mainly used for the SPI interface, QSPI and SD Card over power rails VDDIOP0, VDDQSPI1/0
and VDDSDMMC1, respectively.
The following schematic shows the PIOB bank distribution.
SAMA7G54-EK
Function Blocks
©
2022 Microchip Technology Inc.
and its subsidiaries
User Guide
DS50003273A-page 23