An individual unique 48-bit MAC address (Ethernet hardware address) is allocated to this product and is stored in one
of the Microchip 24AA025E48 TWI serial EEPROMs described in
Additionally, for monitoring and control purposes, the RJ45 connectors feature a LED functionality to indicate activity,
link, and speed status.
Figure 3-32. Gigabit Ethernet Interface Schematic
RJMG2012211A0FR
GA1
14
GC1 13
GREEN (LINK/ACT)
SHIELD1
0
GA2
16
GC2 15
GREEN (Duplex/Collision)
TRD1- 10
TRCT1 12
TRD1+ 11
TRD4- 9
TRCT4 7
TRD4+ 8
TRD2- 5
TRCT2 6
TRD2+ 4
TRD3- 2
TRCT3 1
TRD3+ 3
J5
ETH0_TXEN_PA15
ETH0_TX0_PA16
ETH0_TX1_PA17
ETH0_RX0_PA19
ETH0_RX1_PA20
ETH0_RXCTL_PA18
ETH0_MDC_PA22
ETH0_MDIO_PA23
ETH0_TXCK_PA24
ETH0_125CK_PA25
ETH0_TX2_PA26
ETH0_TX3_PA27
ETH0_RX2_PA28
ETH0_RX3_PA29
ETH0_RXCK_PA30
ETH0_INT_PA31
ETH0_TXRX_A_P
ETH0_TXRX_A_N
ETH0_TXRX_B_P
ETH0_TXRX_B_N
ETH0_TXRX_C_P
ETH0_TXRX_C_N
ETH0_TXRX_D_P
ETH0_TXRX_D_N
1
3
25MHz
ECS-250-20-33-CKM-TR
Y5
GND
GND
20pF
50V
0402
C166
20pF
50V
0402
C165
0402
R165
nRST
GND
ETH0_XI_25M
ETH0_XO_25M
6.04k
0402
1%
R169
i
ETH0
Matched Net Lengths [Tolera
ETH0_LED1
ETH0_LED2
ETH0_LED_MODE
ETH0_LDO_O
10k
0402
1%
R143
10k
0402
1%
R144
10k
0402
1%
R145
1k
0402
5%
R146
1k
0402
5%
R147
1k
0402
5%
R163
10k
0402
1%
R149
10k
0402
1%
R150
10k
0402
1%
R151
10k
0402
1%
R152
10k
0402
1%
R153
VDD_3V3
220R
1%
R142
220R
1%
R162
10uF
10V
0805
C149
120R
BLM18PG121SN1D
FB3
10uF
10V
0805
C167
GND
VDD_3V3
0.1uF
10V
0402
C168
AVDDH
kSZ9131RNXC
AVDDH
1
TXRXP_A
2
TXRXM_A
3
AVDDL
4
TXRXP_B
5
ePAD 49
LDO_O 43
NC 47
INT_N/ALLPHYAD 38
CLK125_NDO/LED_MODE 41
TXRXM_B
6
TXRXP_C
7
TXRXM_C
8
AVDDL
9
MDIO 37
ISET 48
XO 45
XI 46
MDC 36
DVDDH
40
DVDDL
39
AVDDL_PLL
44
TXRXP_D
10
TXRXM_D
11
AVDDH
12
NC 13
NC 14
DVDDH
16
DVDDL
18
RXD3/MODE3 27
RXD2/MODE2 28
RXD1/MODE1 31
RXC/PHYAD2 35
DVDDL
23
TXC 24
TXD3 22
TXD2 21
TXD1 20
TXD0 19
TX_CTL 25
RESET_N 42
RX_CTL/CLK125_EN 33
DVDDL
26
VSS 29
RXD0/MODE0 32
LED1/PME_N1/PHYAD0 17
DVDDL
30
LED2/PHYAD1 15
DVDDH
34
U14
120R
BLM18PG121SN1D
FB4
10uF
10V
0805
C177
GND
VDD_3V3
0.1uF
10V
0402
C178
DVDDH
0.01uF
50V
0402
C150
AVDDH
0.01uF
50V
0402
C151
10uF
10V
0805
C152
0.01uF
50V
0402
C153
0.01uF
50V
0402
C154
0.01uF
50V
0402
C155
DVDDH AVDDL
10uF
10V
0805
C156
0.01uF
50V
0402
C157
0.01uF
50V
0402
C158
AVDDL_PLL
0.01uF
50V
0402
C159
DVDDL
10uF
10V
0805
C160
0.01uF
50V
0402
C162
0.01uF
50V
0402
C163
0.01uF
50V
0402
C164
0.01uF
50V
0402
C169
0.01uF
50V
0402
C170
0.01uF
50V
0402
C171
10uF
10V
0805
C172
GND
GND
GND_ETH0
GND_ETH0
GND
120R
BLM18PG121SN1D
FB2
120R
BLM18PG121SN1D
FB5
10uF
10V
0805
C179
GND
AVDDL
0.1uF
10V
0402
C180
AVDDL_PLL
120R
BLM18PG121SN1D
FB6
10uF
10V
0805
C181
GND
AVDDL
0.1uF
10V
0402
C182
DVDDL
4
1,2,3
5,6,7,8
NDS8434
Q4
10uF 10V 0805
C161
(3V3)
GND
AVDDL
0.1uF
10V
0402
C173
0.01uF
50V
0402
C174
10uF
10V
0805
C175
GND
(1V2)
(1V2)
(1V2)
Pd = (3V3 -1V2) x 0,25 =0.525W
33R
0402 1%
R159
22R
0402 1%
R154
22R
0402 1%
R164
51R
0402
1%
R171
VDD_3V3
STB
1
GND
2
OUT 3
VDD 4
DSC1001DI5-025.0000
Y6
GND
0.1uF
10V
0402
C176
GND
VDD_3V3
0402
R167
0402
R168
ETH0_XI_25M
0402
R166
NRST_OUT
RGMII ETHERNET 1Gbps TRANSCEIVER
TP29
DIFF100
DIFF100
DIFF100
DIFF100
DIFF100
DIFF100
DIFF100
DIFF100
DVDDH
100k
0402 5%
R170
GND
33R
0402 1%
R158
33R
0402 1%
R157
33R
0402 1%
R156
33R
0402 1%
R155
33R
0402 1%
R160
1k
0402
5%
R161
ETH0_LED1
0.1uF
10V
0402
C145
0.1uF
10V
0402
C146
0.1uF
10V
0402
C147
0.1uF
10V
0402
C148
VDD_3V3
ETH0_LED2
10k
0402
1%
R148
100
Ω
±10% differential trace impedance
Routing top or bottom
50
Ω
± 10% single-ended trace impedance
Table 3-20. Gigabit Ethernet Interface Schematic
PIO
Signal Name
Shared With
Signal Description
PA15
ETH0_TXEN_PA15
–
Transmit enable
PA16
ETH0_TX0_PA16
–
Transmit data line 0
PA17
ETH0_TX1_PA17
–
Transmit data line 1
PA18
ETH0_RXCTL_PA18
–
Receive data valid or carrier sense and data valid
PA19
ETH0_RX0_PA19
–
Receive data line 0
PA20
ETH0_RX1_PA20
–
Receive data line 1
PA22
ETH0_MDC_PA22
–
Management data clock
PA23
ETH0_MDIO_PA23
–
Management data input/output
PA24
ETH0_TXCK_PA24
–
Transmit clock or 50 MHz reference clock
PA25
ETH0_125CK_PA25
–
125 MHz clock
PA26
ETH0_TX2_PA26
–
Transmit data line 2
PA27
ETH0_TX3_PA27
–
Transmit data line 3
PA28
ETH0_RX2_PA28
–
Receive data line 2
PA29
ETH0_RX3_PA29
–
Receive data line 3
PA30
ETH0_RXCK_PA30
–
Receive clock
PA31
ETH0_INT_PA31
–
Ethernet 0 interrupt
SAMA7G54-EK
Function Blocks
©
2022 Microchip Technology Inc.
and its subsidiaries
User Guide
DS50003273A-page 42