Figure 3-14. DDR_VREF Voltage Reference
1k
0201
1%
R106
1k
0201
1%
R108
GND
4.7uF
10V
0402
C114
GND
DDR_VREF
0.1uF
16V
0201
C110
0.1uF
16V
0201
C118
VDDIODDR
3.2.5
Processor PIOs
This section describes all the signals connected to the SAMA7G5 MPU ports.
Some of the ports are multiplexed to accommodate more devices on the evaluation kit and to showcase all the
functions the SAMA7G5 MPU can address off a single PIO wire. Most of the ports that share multiple functions are
split through passive resistors placed on the board as close to the MPU as possible, therefore no other hardware
change must be made. In most cases, the user can use only one of their functions at a time, or develop a composite
driver enabling the use of multiple functions at the same time.
3.2.5.1
PIOA Bank
The PIOA bank is mainly used for the e.MMC memory and Gigabit Ethernet over power rails VDDSDMMC0 and
VDDIOP0, respectively.
The following schematic shows the PIOA bank distribution.
SAMA7G54-EK
Function Blocks
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2022 Microchip Technology Inc.
and its subsidiaries
User Guide
DS50003273A-page 21