Figure 3-13. Processor UDDRC Controller
DDR_RESET
DDR_ZQ
DDR_DQM0
DDR_VREF
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_DQM1
DDR_DQS0_P
DDR_DQS0_N
DDR_DQS1_P
DDR_DQS1_N
i
LANE0
Matched Net Lengths [Tolerance = 10mil]
i
LANE1
Matched Net Lengths [Tolerance = 10mil]
240R
0201
1%
R105
0.1uF
16V
0201
C103
GND
GND
100k
0201
1%
R104
VDDIODDR
DDR_A0
DDR_BA0
DDR_ODT
DDR_CK_P
DDR_CK_N
DDR_CKE
DDR_WE
DDR_CS
i
ADDR-CTL
Matched Net Lengths [Tolerance = 10mil]
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_A14
DDR_A15
DDR_BA1
DDR_BA2
DDR_RAS
DDR_CAS
GND
VDDIODDR
0.1uF
16V
0201
C104
0.1uF
16V
0201
C105
0.1uF
16V
0201
C106
0.1uF
16V
0201
C107
0.1uF
16V
0201
C108
0.1uF
16V
0201
C109
0.1uF
16V
0201
C111
0.1uF
16V
0201
C112
0.1uF
16V
0201
C113
0.1uF
16V
0201
C115
0.1uF
16V
0201
C116
0.1uF
16V
0201
C117
0.1uF
16V
0201
C119
0.1uF
16V
0201
C120
4.7uF
10V
0402
C122
GND
DIFF100
DIFF100
DIFF100
DIFF100
DIFF100
DIFF100
SAMA7G5 DDR3-1066 controller
(1V35)
(1V35)
0.1uF
16V
0201
C121
DDR_A0
W6
DDR_A1
P6
DDR_A2
V5
DDR_A3
V6
DDR_A4
R6
DDR_A5
W4
DDR_A6
P7
DDR_A7
W2
DDR_A8
L8
DDR_A9
V4
DDR_A10
T3
DDR_A11
M9
DDR_A12
P5
DDR_A13
V2
DDR_BA0
V8
DDR_BA1
P4
DDR_BA2
R8
DDR_RAS#
U8
DDR_CAS#
T8
DDR_CLK_P
U4
DDR_CLK_N
T4
DDR_CKE
V3 DDR_CS#
V7
DDR_WE#
N10
DDR_ZQ AA2
DDR_RESET# V1
DDR_D0 N2
DDR_D1 M7
DDR_D2 R3
DDR_D3 M8
DDR_D4 T2
DDR_D5 N8
DDR_D6 T1
DDR_D7 N7
DDR_D8 Y7
DDR_D9 AA4
DDR_D10 Y9
DDR_D11 Y3
DDR_D12 AA7
DDR_D13 AA3
DDR_D14 W7
DDR_D15 W3
DDR_DQM0 N1
DDR_DQM1 Y4
DDR_DQS0_P R1
DDR_DQS0_N R2
DDR_DQS1_P Y6
DDR_DQS1_N AA6
DDR_ODT
W1
DDR_VREF Y1
DDR_A14
L9
DDR_A15
R4
GNDIODDR L7
GNDIODDR L11
GNDIODDR N4
GNDIODDR P1
GNDIODDR P8
GNDIODDR R5
GNDIODDR R7
GNDIODDR T5
GNDIODDR U1
GNDIODDR U7
GNDIODDR V9
GNDIODDR AA1
VDDIODDR
AA5
GNDIODDR AA8
GNDIODDR AA11
VDDIODDR
N6
VDDIODDR
N9
VDDIODDR
P3
VDDIODDR
T6
VDDIODDR
T7
VDDIODDR
T9
VDDIODDR
U3
VDDIODDR
U5
VDDIODDR
U6
GNDIODDR W5
VDDIODDR
Y2
VDDIODDR
N12
VDDIODDR
P13
VDDIODDR
W8
VDDIODDR
M11
SAMA7G54
U4F
SAMA7G54
100
Ω
±10% differential trace impedance
Routing top or bottom
50
Ω
± 10% single-ended trace impedance
Routing top or bottom
100
Ω
±10% differential trace impedance
Routing top or bottom
50
Ω
± 10% single-ended trace impedance
Routing top or bottom
50
Ω
± 10% single-ended trace impedance
Routing top or bottom
100
Ω
±10% differential trace impedance
Routing top or bottom
RZQ: calibration capability for on-die
terminations and driver output impedances
The UDDRC I/Os embed an automatic impedance matching control to avoid overshoots and to reach the best
performance levels depending on the bus load and external memories. A serial termination connection scheme,
where the driver has an output impedance matched to the characteristic impedance of the line, is used to improve
signal quality and reduce EMI. This is done using the ZQ calibration procedure to calibrate the SAMA7G5 DDR
I/O drive strength. The pin name where the ZQ resistor must be connected is DDR_ZQ, and as indicated in the
SAMA7G5 Series data sheet for the DDR3L case, the resistor value is 240 Ohms.
The DDR_VREF pin serves as a voltage reference input for the DDR I/Os when DDR or LPDDR external SDRAM
memories are used.
SAMA7G54-EK
Function Blocks
©
2022 Microchip Technology Inc.
and its subsidiaries
User Guide
DS50003273A-page 20
