Table 3-11. Second SPI PIO Assignment
PIO MPU Net Name
Device Net Name
Function
PE3 PE3
EXT40_SPI1_MOSI_PE3
SPI MOSI line RPi 40-pin connector
BT_RX_FLEXCOM0_IO0_PE3
WILC3000 USART RX line
PE4 PE4
EXT40_SPI1_MISO_PE4
SPI MISO line RPi 40-pin connector
BT_TX_FLEXCOM0_IO1_PE4
WILC3000 USART TX line
PE6 PE6
EXT40_SPI1_CE0_PE6
SPI Chip Select 0 RPi 40-pin connector
BT_RTS_FLEXCOM0_IO3_PE6
WILC3000 USART RTS line
PE7 PE7
EXT40_SPI1_CE1_PE7
SPI Chip Select 1 RPi 40-pin connector
BT_CTS_FLEXCOM0_IO4_PE7
WILC3000 USART CTS line
PE5 EXT40_SPI1_SCLK_PE5
EXT40_SPI1_SCLK_PE5
SPI clock line RPi 40-pin connector
3.2.5.6.3 GPIO Distribution
The SAMA7G54-EK features one QuickSwitch 2:1 multiplexer to distribute the MPU PIOs.
The multiplexer distributes the PIOs according to the J3 status:
• J3 is open (default mode): the Ethernet 10/100 interface is distributed.
• J3 is closed: the PDMC0 interface is distributed.
Figure 3-25. GPIO Distribution Schematic
S
1
I0A 2
I1A 3
YA
4
I0B 5
I1B 6
YB
7
GND 8
YC
9
I1C 10
I0C 11
YD
12
I1D 13
I0D 14
E
15
VCC 16
IDTQS3VH257PAG
U5
PD22
PD23
PD24
ETH1_TX0_PD22
GND
GND
0.1uF
10V
0402
C82
VDD_3V3
PDMC0_CLK_PD22
ETH1_TX1_PD23
PDMC0_DS0_PD23
ETH1_CRSDV_PD24
PDMC0_DS1_PD24
10k
0402
1%
R93
GND
VDD_3V3
1
2
HDR-2.54 Male 1x2
J3 JP2
EN_PDMC
Table 3-12. GPIO Assignments
PIO
MPU Net Name
Device Net Name
Function
PD22
PD22
ETH1_TX0_PD22
Transmit data line 0
PDMC0_CLK_PD22
PDM clock line
PD23
PD23
ETH1_TX1_PD23
Transmit data line 1
PDMC0_DS0_PD23
PDM data line 0
SAMA7G54-EK
Function Blocks
©
2022 Microchip Technology Inc.
and its subsidiaries
User Guide
DS50003273A-page 33