Figure 3-5. Power Management Unit Schematic
GND
GND
GND
GND
4.7uF
10V
0402
C1
4.7uF
10V
0402
C5
4.7uF
10V
0402
C11
4.7uF
10V
0402
C15
GND
5V_MAIN
5V_MAIN
5V_MAIN
5V_MAIN
GND
5V_MAIN
VDD_3V3
VDD_3V3
22uF
10V
0603
C2
22uF
10V
0603
C6
22uF
10V
0603
C12
22uF
10V
0603
C16
MCP16502_INT_PD9
nRST
WKUP
SHDN
nSTART
1.5uH
DFE252012P-1R5M=P2
L1
1.5uH
DFE252012P-1R5M=P2
L2
1.5uH
DFE252012P-1R5M=P2
L3
1.5uH
DFE252012P-1R5M=P2
L4
TP1
4.7uF
10V
0402
C17
4.7uF
10V
0402
C19
4.7uF
10V
0402
C20
(5V0)
(5V0)
(5V0)
max 1A
max 1A
max 1A
max 0.3A
max 0.3A
max 1A
LPM
5V_MAIN
TP9
GND
(5V0)
10k
0402
1%
R4
0R
0603
R2
1k
0402
5%
R3
VDD_1V35
VDD_1V15_OUT3
VDD_1V15_OUT4
VLDO2
VLDO1
MCP16502_TWD
MCP16502_TWCK
MCP16502TAB-E/S8B
PVIN2 15
PVIN1 10
PVIN3 26
PVIN4 31
PGND2 13
PGND3 28
PGND4 29
PGND1 12
SW1 11
SW2 14
SW3 27
SW4 30
OUT1 9
OUT2 16
OUT3 25
OUT4 32
SVIN
4
SGND
3
LVIN 20
LOUT1 19
LOUT2 21
SELVL1
18
nSTRT
24
SCL
6
SDA
5
nINTO
1
nRSTO
2
nSTRTO
7
HPM
23
PWRHLD
8
LPM
22
SELV2
17
EP
33
U1
5V_MAIN
GND
10k
0402
1%
R10
10k
0402
1%
R11
TP3
TP5
TP6
TP8
(5V0)
TP7
(3V3)
(1V35)
(1V15)
(1V15@800MHz)
(1V8)
(OFF)
PMIC
10k
0402
1%
R5
VDDBU
100k
0402
5%
R6
4.7uF
10V
0402
C18
0R
0603
R1
(1V25@1000MHz)
HPM_PB15
3
1
2
BSS138N
Q3
10k
0402
1%
R12
VDD_3V3
LPM
GND
OSC_STBY
Selected 1.35V for
OUT2 as default
Selected 1.8V for
VLDO1 as default
Table 3-1. MCP16502 TWI Address
Device
7-bit client address
Full Address with RD/WR#
MCP16502 TWI Read
1011_011
0xB7
MPC16502 TWI Write
0xB6
3.1.3
Shutdown and Reset Circuitry
The processor controls the Auto-Maintain state and power-down by asserting the SHDN pin. At power-up, the SHDN
signal is asserted at high level, sending the instruction to maintain power to the PMIC device. At power-down, SHDN
is asserted at low level, PMIC shuts down all the supplies and enters Power-down mode.
The board includes three reset sources for the SAMA7G5 MPU:
• Power-on reset from the MCP16502 power management unit
• User push button reset (SW2)
• External JTAG or J-Link-OB reset from an in-circuit emulator
Some elements on the board (such as Ethernet PHYs, octal SPI memory and mikroBUS sockets) can be reset by the
MPU independently from the general reset. They are connected by default to the NRST_OUT signal of the SAMA7G5
device and each of them can be controlled by the general reset line. A resistor swap must be performed for this
configuration.
The figure below shows the shutdown connection and the reset circuitry.
SAMA7G54-EK
Function Blocks
©
2022 Microchip Technology Inc.
and its subsidiaries
User Guide
DS50003273A-page 12