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10.2
Redundancy BMS
The redundancy BMS has thresholds that are beyond the regular slave BMS thresholds stated in
section 10.1. When a critical redundancy BMS level is triggered, the master is informed that the
hard-wired interlock will be interrupted after 15 seconds. The Master BMS will go to fail-safe once
the hard-wired interlock loop is interrupted.
Cell voltage
Table 22 Cell voltage boundary limits redundancy unit BMS
Boundary condition
Name
Level
Default
Performance
Time
Hardware failure warning
Set
= invalid
1 sec.
Clear
= valid
1 sec.
Sensor failure critical
Interrupt
HVIL
= invalid
75 sec.
Over voltage warning
Set
>= 4400 mV
1 sec.
Clear
< 4400 mV
1 sec.
Over voltage critical
Interrupt
HVIL
>= 4400 mV
40 sec.
Under voltage warning
Set
<= 2200 mV
1 sec.
Clear
> 2200 mV
1 sec.
Under voltage critical
Interrupt
HVIL
<= 2200 mV
40 sec.
Cell temperature
Table 23 Cell temperature boundary limits redundancy unit BMS
Boundary condition
Name
Level
Default
Performance
Time
Sensor failure warning
Set
= invalid
1 sec.
Clear
= valid
1 sec.
Sensor failure critical
Interrupt
HVIL
2 are more temperature sensor
invalid
75 sec.
Over temperature warning
Set
>= 65 °C
1 sec.
Clear
< 65 °C
1 sec.
Over temperature critical
Interrupt
HVIL
>= 65 °C
75 sec.
Under temperature warning
Set
<= -38 °C
1 sec.
Clear
> -38 °C
1 sec.
Under temperature critical
Interrupt
HVIL
<= -38 °C
75 sec.