SDRAM Interface Functional Overview
ECC Support
Copyright © 2002 Marvell
CONFIDENTIAL
Doc. No. MV-S300165-00, Rev. A
May 21, 2002, Preliminary
Document Classification: Proprietary Information
Page 41
case, the ECC error address register latches the first event address. The Interrupt Service Routine (ISR)
can easily detect if the first event is the latched event with one or two errors by clearing the ECC error
address register and then reading the latched address. If the address is latched again, the first event was
two errors since the SDRAM controller did not fix the error. If the address is not latched, the first event was
one ECC error but the SDRAM controller fixed it.
4.5.1 ECC Bank Initialization
To work with the ECC support, the ECC bank must be initialized.
Use one of the following procedures to initialize the ECC bank.
SDRAM Size Is Known
Note
Useful when SDRAM devices are assembled on board.
1.
When running code from the boot device, configure the address space of the SDRAM interface to fit
the memory size and configuration (all physical banks must be initialized). For more information on
the address decode settings, see the GT-64260A datasheet’s "Address Space Decoding" section.
2.
Set to ‘0’ the SDRAM ECC Control register’s
ErrProp
bit [9] and the
ThrEcc
bits [23:16], at offset
0x494. This prevents the GT-64260A from generating an interrupt or propagating the ECC error to
other interfaces.
3.
In the SDRAM Timing Parameters register, at offset 0x4b4, set the
ECCEn
bit [13] to ’1’ and the
RdSample
bit [14] to ‘0’.
4.
Perform 64-bit or burst write transactions to all of the memory space. Use IDMA engines to shorten
the initialization sequence (e.g., copy the SDRAM to itself and use a data transfer limit of 128B).
5.
To clear the ECC error report, write 0x0 to the SDRAM Error Address register’s
ErrType
bits [1:0],
at offset: 0x490.
6.
Set to a value other than ’0’ (depending on the SW architecture) the
ErrProp
bit [9] and the
ThrEcc
bits [23:16] in the SDRAM ECC Control register. This enables the ECC interrupt to be generated
and/or propagates the error to other interfaces.
SDRAM Size Is Flexible and Can Be Changed
Note
Useful when SDRAM devices are assembled on DIMM connectors.
1.
When running code from the boot device, configure an address space in the SDRAM interface
needed for the first operation of the operating system. For more information on the address decode
settings, see the GT-64260A datasheet’s "Address Space Decoding" section.
2.
Set the SDRAM ECC Control register’s
ErrProp
bit [9] and the
ThrEcc
bits [23:16], at offset 0x494
to ‘0’. This prevents the GT-64260A from generating an interrupt or propagating the ECC error to
other interfaces.
3.
In the SDRAM Timing Parameters register, at offset 0x4b4, set the
ECCEn
bit [13] to ’1’ and the
RdSample
bit [14] to ‘0’.
4.
Perform 64-bit or burst write transactions to the memory space defined in step 1. It is recommended
to use IDMA engines to shorten the initialization sequence (e.g., copy the SDRAM to itself and use a
Data Transfer Limit of 128B).
