GT-64260A Design Guide
Doc. No. MV-S300165-00, Rev. A
CONFIDENTIAL
Copyright © 2002 Marvell
Page 34
Document Classification: Proprietary Information
May 21, 2002, Preliminary
DAdr[12:0]
t/s O
When using DRAM DIMMs,
connect to the DAdr pins.
When using SDRAM
devices, must be connected
to the DAdr pins of each
device.
When using 16 Mb devices,
use only Dadr[10:0].
When using 64 or 128 Mbit
devices, use only Dadr[11:0].
When using 256 or 512 Mb
devices, use only Dadr[12:0].
10K-Ohm pull up is
required only in UMA
mode.
SDRAM Address
NOTE:
For more information
on the address connection,
see
This pin is tri-stated only in
UMA mode.
BankSel[1:0]
t/s O
When using DRAM DIMMs,
connect to the BankSel pins.
When using SDRAM,
devices must be connected
to BankSel pins of each
device.
When using 16 Mb devices,
use only BankSel [0].
When using 64, 128, 256 or
512 Mbit devices, only use
BankSel [1:0].
10K-Ohm pull up is
required only in UMA
mode.
SDRAM Bank Select.
NOTE:
For more information
on the address connection,
see
These pins are tri-stated
only in UMA mode.
SCS[3:0]*
t/s O
Each SCS* pin must select
64-bits wide data + 8-bits
ECC (if used).
When using DRAM DIMM,
connect to the physical bank
(CS0* and CS2*) or (CS1*
and CS3*) pins, because
each one selects only 32-bit
data width.
When using SDRAM
devices, must be connected
to CS* pin of each device. All
devices connected to the
same SCS* pin must be con-
nected in parallel to achieve
64-bit wide data.
10K-Ohm pull up is
required only in UMA
mode.
SDRAM Chip Select
These pins are tri-stated
only in UMA mode.
SDQM[7:0]*
t/s O
When using DRAM DIMMs,
connect to the SDQM pins.
When using SDRAMs,
devices must be connected
to the SDQM pin of each
device.
In UMA mode the
master must drive
these pins.
SDRAM Data Mask.
Table 7:
SDRAM Interface Pinout Description (Continued)
Pin Name
Input/
Output
SDRAM Device or
DIMM Connector
Required
External
Resistor
Description