LabJack LJU3-LV, Руководство пользователя

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Command:
Byte
0 Checksum8
1 0xF8
2 4 + NumSPIWords
3 0x3A
4 Checksum16 (LSB)
5 Checksum16 (MSB)
6 SPIOptions
Bit 7: AutoCS
Bit 6: DisableDirConfig
Bits 1-0: SPIMode (0=A, 1=B, 2=C, 3=D)
7 SPIClockFactor
8 Reserved
9 CSPinNum
10 CLKPinNum
11 MISOPinNum
12 MOSIPinNum
13 NumSPIBytesToTransfer
14 SPIByte0
... ...
Response:
Byte
0 Checksum8
1 0xF8
2 1 + NumSPIWords
3 0x3A
4 Checksum16 (LSB)
5 Checksum16 (MSB)
6 Errorcode
7 NumSPIBytesTransferred
8 SPIByte0
... ...
NumSPIWords : This is the number of SPI bytes divided by 2. If the number of SPI bytes is odd, round up and add an extra
zero to the packet.
SPIOptions : If AutoCS is true, the CS line is automatically driven low during the SPI communication and brought back high
when done. If DisableDirConfig is true, this function does not set the direction of the lines, whereas if it is false the lines are
configured as CS=output, CLK=output, MISO=input, and MOSI=output. SPIMode specifies the standard SPI mode as
discussed below.
SPIClockFactor : Sets the frequency of the SPI clock. A zero corresponds to the maximum speed of about 80kHz and 255
the minimum speed of about 5.5kHz.
CS/CLK/MISO/MOSI -PinNum : Assigns which digital I/O line is used for each SPI line. Value passed is 0-19 corresponding
to the normal digital I/O numbers as specified in Section 2.8.
NumSPIBytesToTransfer : Specifies how many SPI bytes will be transferred (1-50).
The initial state of SCK is set properly (CPOL), by this function, before CS (chip select) is brought low (final state is also set
properly before CS is brought high again). If CS is being handled manually, outside of this function, care must be taken to make
sure SCK is initially set to CPOL before asserting CS.
All standard SPI modes supported (A, B, C, and D).
Mode A: CPOL=0, CPHA=0
Mode B: CPOL=0, CPHA=1
Mode C: CPOL=1, CPHA=0
Mode D: CPOL=1, CPHA=1
If Clock Phase (CPHA) is 1, data is valid on the edge going to CPOL. If CPHA is 0, data is valid on the edge going away from
CPOL. Clock Polarity (CPOL) determines the idle state of SCK.
Up to 50 bytes can be written/read. Communication is full duplex so 1 byte is read at the same time each byte is written.
5.2.16 - AsynchConfig
Requires U3 hardware version 1.21+. Configures the U3 UART for asynchronous communication. On hardware version 1.30 the
TX (transmit) and RX (receive) lines appear on FIO/EIO after any timers and counters, so with no timers/counters enabled, and pin
offset set to 4, TX=FIO4 and RX=FIO5. On hardware version 1.21, the UART uses SDA for TX and SCL for RX. Communication is
in the common 8/n/1 format. Similar to RS232, except that the logic is normal CMOS/TTL. Connection to an RS232 device will
require a converter chip such as the MAX233, which inverts the logic and shifts the voltage levels.
Command:
Byte
0 Checksum8
1 0xF8
2 0x02
3 0x14
4 Checksum16 (LSB)
5 Checksum16 (MSB)
6 0x00
7 AsynchOptions
Bit 7: Update
Bit 6: UARTEnable
Bit 5: Reserved
8 BaudFactor LSB (1.30 only)
9 BaudFactor MSB
Response:
Byte
0 Checksum8
1 0xF8
2 0x02
3 0x14
4 Checksum16 (LSB)
5 Checksum16 (MSB)
6 Errorcode
7 AsynchOptions
8 BaudFactor LSB (1.30 only)
9 BaudFactor MSB
AsynchOptions :
Bit 7: Update If true, the new parameters are written (otherwise just a read is done).
Bit 6: UARTEnable If true, the UART module is enabled. Note that no data can be transfered until pins have been assigned
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