Intended for frequencies less than 10 Hz, this mode adds a debounce feature to the firmware counter, which is particularly useful
for signals from mechanical switches. On every applicable edge seen by the external pin, this mode increments a 32-bit register.
Unlike the pure hardware counters, these timer counters require that the firmware jump to an interrupt service routine on each
edge.
The debounce period is set by writing the timer value. The low byte of the timer value is a number from 0-255 that specifies a
debounce period in 16 ms increments (plus an extra 0-16 ms of variability):
Debounce Period = (0-16 ms) + (TimerValue * 16 ms)
In the high byte (bits 8-16) of the timer value, bit 0 determines whether negative edges (bit 0 clear) or positive edges (bit 0 set) are
counted.
Assume this mode is enabled with a value of 1, meaning that the debounce period is 16-32 ms and negative edges will be
counted. When the input detects a negative edge, it increments the count by 1, and then waits 16-32 ms before re-arming the edge
detector. Any negative edges within the debounce period are ignored. This is good behavior for a normally-high signal where the
switch closure causes a brief low signal (Figure 2-10). The debounce period can be set long enough so that bouncing on both the
switch closure and switch open is ignored.
Writing a value of zero to the timer performs a reset. After reset, a read of the timer value will return zero until a new edge is
detected. If a timer is reset and read in the same function call, the read returns the value just before the reset.
2.9.1.7 - Frequency Output (Mode 7)
Outputs a square wave at a frequency determined by TimerClockBase/TimerClockDivisor divided by 2*Timer#Value. The Value
passed should be between 0-255, where 0 is a divisor of 256. By changing the clock configuration and timer value, a wide range
of frequencies can be output, as shown in the following table:
Mode 7 Frequency Ranges
Divisor=1
Divisor=1
TimerClockBase
Value=1
Value=256
0
4 MHz
2000000
7812.5
1
12 MHz
6000000
23437.5
2
48 MHz (default)
24000000
93750
Divisor=1
Divisor=256
Value=1
Value=256
3
1 MHz /Divisor
500000
7.629
4
4 MHz /Divisor
2000000
30.518
5
12 MHz /Divisor
6000000
91.553
6
48 MHz /Divisor
24000000
366.211
Table 2.9.1.7-1. Mode 7 Frequency Ranges
Note that the clocks above apply to the U3 hardware revision 1.21. With hardware revision 1.20 all clocks are half of those values.
The frequency output has a -3 dB frequency of about 10 MHz on the FIO lines. Accordingly, at high frequencies the output
waveform will get less square and the amplitude will decrease.
The output does not necessarily start instantly, but rather waits for the internal clock to roll. For example, if the output frequency is
100 Hz, that means the period is 10 milliseconds, and thus after the command is received by the device it could be anywhere from
0 to 10 milliseconds before the start of the frequency output.
Frequency List for U3 Timer Mode 7
CSV list of the 262,144 possible frequency output options on the U3 hardware rev 1.21+. Columns are Hz, base clock, clock
divisor, and timer value. Oct 27, 2008.
File attachment:
U3_FreqOutList_Hz_Base_Divisor_Value.csv
2.9.1.8 - Quadrature Input (Mode 8)
Requires both timers, where Timer0 will be quadrature channel A, and Timer1 will be quadrature channel B. The U3 does 4x
quadrature counting, and returns the current count as a signed 32-bit integer (2’s complement). The same current count is returned
on both timer value parameters.
Writing a value of zero to either or both timers performs a reset of both. After reset, a read of either timer value will return zero until
a new quadrature count is detected. If a timer is reset and read in the same function call, the read returns the value just before the
reset.
4X Counting
Quadrature mode uses the very common 4X counting method, which provides the highest resolution possible. That means you get
a count for every edge (rising & falling) on both phases (A & B). Thus if you have an encoder that provides 32 PPR, and you rotate
that encoder forward 1 turn, the timer Value register will be incremented by +128 counts.
Z-phase support
Quadrature mode supports Z-Phase. When enabled this feature will set the count to zero when the specified IO line sees a logic
high.
Z-phase is controlled by the value written to the timer during initialization. To enable z-phase support set bit 15 to 1 and set bits 0
through 4 to the DIO number that Z is connected to. EG: for a Z-line on EIO3 set the timer value to 0x800B or 32779. This value
should be sent to both the A and B timers.
Note that the LabJack will only check Z when it sees an edge on A or B.
Z-phase support requires Firmware 1.30 or later.
2's Complement
Other timer modes return unsigned values, but this timer mode is unique in that it returns a signed value from -2147483648 to
+2147483647. That is, a 32-bit 2's complement value. When you do a timer value read and get back a single float from the UD
driver, the math is already done and you get back a value from -2147483648.0 to +2147483647.0, but when using the special
channels 20x/23x/224 you get the LSW and MSW separately and have to do the math yourself. Search for 2's complement math
for your particular programming language.
In a language such as C++, you start by doing using unsigned 32-bit variables & constants to compute Value = (MSW * 65536) +
LSW. Then simply cast Value to a signed 32-bit integer.
In a language such as Java that does not support unsigned integers, do everything with signed 64-bit variables & constants. First
calculate Value = (MSW * 65536) + LSW. If Value < 2147483648, you are done. If Value >= 2147483648, do ActualValue = -1 *
(4294967296 - Value).
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