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Kendrion Kuhnke Automation GmbH
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11/25/2016
4.15.3.8 Analog Inputs / Oversampling
The samples of the analog inputs are cyclically determined on the module and provided in variables for
pickup by the EtherCAT master. For the evaluation of an analog value pattern both the cycle time of the
analog conversions and the EtherCAT cycle play a role.
For an accurate assessment the module provides oversampling with adjustable parameters. There are two
methods of control that can be selected already in the configurator.
SM-Synchronous (SM=Sync-Master)
DC-Synchronous (DC=Distributed Clocks)
4.15.3.8.1 Analog Inputs / Oversampling SM-Synchronous
The module measures every millisecond 4 analog values. Depending on the setting of the oversampling
parameter (object index 0x2000) these values are copied into the process image. The default is 5.
In this setting, the analog process image will be updated after 5ms (indicated by the incremented counter
Inputs, Sample Cycle Counter).
The millisecondly measured values are respectively in Sample0..4 of the variables from AnalogIn0 ..
AnalogIn4.
If the parameter is smaller, the process image is updated accordingly faster and the unused sample values
remain empty.
Example:
If the oversampling parameter is 1, a new process image is generated after 1 millisecond.
The values are then only on Sample0. Sample 1..4 are unused.
4.15.3.8.2 Oversampling DC-Synchronous
The SYNC0 interrupt is used for analog measurement and the SYNC1 Interrupt for transmitting the data to
the process image.
SYNC0 may be faster by a factor of 1 to 5 than SYNC1.
Example1:
Bus Cycle is 5ms. "DC synchron 5 x oversampling" is set.
This Sync1 is triggered every 5ms and SYNC0 all 1ms.
The analog values are therefore measured every millisecond and copied after 5ms to the process image in
Sample 0-4
. The
SampleCycleCounte
r is incremented after 5ms.
Example2:
Bus Cycle is 2ms. "DC synchron 4 x oversampling" is set.
This Sync1 is triggered every 2ms and SYNC0 all 0.5ms.
The analog values are therefore measured every half millisecond and copied after 2ms to the process image
in
Sample 0-3
.
Sample4
remains empty. The
SampleCycleCounter
is incremented after 2ms.
Example 3:
Bus Cycle is 1ms. "DC synchron”