SP-5000M-PMCL / SP-5000C-PMCL
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6.3.2 Vertical timing
Figure 17 shows the vertical timing of Camera Link output during continuous trigger operation.
However, with 1X8-1Y 10-bit and 1X10–1Y 8-bit geometries, which are 80-bit configurations,
DVAL and Exposure Active, which are normally output to Camera Link spare bits, are not output
through the Camera Link interface as data bits are applied to those bits.
In the SP-5000M-PMCL, H-Binning and V-Binning functions are available but H-Binning function
does not make the frame rate faster.
FVAL
LVAL
DVAL
DATA
Exposure
Active
(Camera Link
“
Spare
”
bit)
Exposure time (Min)
FVAL Active (A)
(B)
(C) V-Offset
0 Line
DVAL Active (A)
(F) Exposure End to FVAL Active Start
(E) Exposure time (Max)
(D)
Fig. 17 Vertical timing
In the SP-5000-PMCL, if the trigger overlap is set to “Readout”, the image readout is
stopped at the start point of the exposure and delayed in order to avoid interference
from the exposure. Therefore, the FVAL Active period is extended by the period for
which the readout has been stopped.
Table 23. FVAL Active extended time if FVAL Active is overlapped
Tap Geometry
Camera Link
Clock
Exposure Active
– At FVAL Active Overlap,
FVAL Active extended time
[Unit: us]
[Unit: Line]
1X10-1Y
82.3 MHz
55.60
16
75.4 MHz
55.40
16
61.7 MHz
67.70
16
1X8-1Y
82.3 MHz
63.40
16
75.4 MHz
69.10
16
61.7 MHz
84.10
16
1X4-1Y
82.3 MHz
125.40
16
75.4 MHz
136.60
16
61.7 MHz
167.40
16
1X2-1Y
82.3 MHz
250.00
16
75.4 MHz
273.00
16
61.7 MHz
333.50
16
