SP-5000M-PMCL / SP-5000C-PMCL
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5.3.7.2 Input and output matrix table
The relation between input and output is as follows.
Table-9 GPIO matrix table
Selector (Cross
point switch output)
Source signal
(Cross point switch input)
Low
High
Soft Trigger
Exposure Active
Frame Trigger Wait
Frame Active
FVAL
LVAL
Pulse Generator 0
Pulse Generator 1
Pulse Generator 2
Pulse Generator 3
Line 4 - TTL In1
Line 7 - CL CC1 in
NAND 0 Out
NAND 1 Out 1
Line 10 - TTL 2 In
Line 11 - LVDS 1 In
Trigger Source
Line Selector
Pulse Generator
Selector
T
ri
gg
er
S
ou
rc
e
(F
ra
m
e
St
ar
t
)
Li
ne
1
-
1
2P
T
T
L
O
ut
Li
ne
8
-
T
T
L
2
O
ut
Trigger Selector
Pulse Generator
Clear Source
Line Source
Li
ne
9
-
T
T
L
3
O
ut
N
A
N
D
1
I
n
1
N
A
N
D
1
I
n
2
N
A
N
D
2
I
n
1
N
A
N
D
2
I
n
2
Pu
ls
e
G
en
er
at
or
0
Pu
ls
e
G
en
er
at
or
1
Pu
ls
e
G
en
er
at
or
2
Pu
ls
e
G
en
er
at
or
3
Note: In the above table, TTL 2 IN, LVDS IN, TTL 2 Out and TTL 3 Out are available only if AUX Type
3 option is used.
5.4 Pulse Generator
The SP-5000-PMCL has a frequency divider using the sensor clock as the basic clock and four pulse
generators. In each Pulse Generator, various Clear settings are connected to GPIO.
The following shows Pulse Generator default settings.