Intel 82562EX, Руководство по конструкции

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82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide
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K10 1.2 V 1.5 V VCC X X 1.2 V 1.5 V 3.3 V Core Power
Plane
K11 1.2 V 1.5 V VCC X X 1.2 V 1.5 V 3.3 V Core Power
Plane
K12 AVSS VSS VSSP X X VSS VSS VSS AVSS = VSSP
= VSS
K13 3.3 V 3.3 V VCC X X 3.3 V 3.3 V 3.3 V VCCP = 3.3 V
K14 XTAL1 XTAL1 X1
L1 AD[14] AD[14] NC X AD[14] AD[14] AD[14]
L2 AD[15] AD[15] NC X AD[15] AD[15] AD[15]
L3 C/BE#[1] C/BE#[1] NC X C/BE#[1] C/BE#[1] C/BE#[1]
L4 1.2 V 1.5 V 3.3 V X X 1.2 V 1.5 V 3.3 V Core Power
Plane
L5 1.2 V 1.5 V 3.3 V X X 1.2 V 1.5 V 3.3 V Core Power
Plane
L6 VSS VSS VSS X X VSS VSS VSS VSSA = VSS
L7 RVSD_NC CLK_BYP# ADV10 X X NC NC NC
L8 NC 2.5 V NC X 1.8V 2.5 V No stuff PHY Power
Plane
L9 1.2 V 1.5 V 3.3 V X X 1.2 V 1.5 V 3.3 V Core Power
Plane
L10 1.2 V 1.5 V 3.3 V X X 1.2 V 1.5 V 3.3 V Core Power
Plane
L11 VSS VSS VSS X X VSS VSS VSS VSSP = VSS
L12 JTAG_TMS JTAG_TMS NC X NC NC NC
L13 JTAG_TRST# JTAG_TRST# JTXD[1] X X LCI LCI LCI ICH drives this
signal low.
TRST needs to
be grounded to
disable JTAG.
JTAG becomes
difficult to use.
L14 JTAG_TCK JTAG_TCK JTXD[2] X X LCI LCI LCI ICH drives this
signal low. TCK
needs to be
biased. JTAG
becomes
difficult to use.
M1 AD[11] AD[11] NC X AD[11] AD[11] AD[11]
M2 AD[12] AD[12] NC X AD[12] AD[12] AD[12]
M3 AD[13] AD[13] NC X AD[13] AD[13] AD[13]
M4 C/BE#[0] C/BE#[0] NC X C/BE#[0] C/BE#[0] C/BE#[0]
M5 AD[5] AD[5] NC X AD[5] AD[5] AD[5]
M6 VSS VSS VSSA X X VSS VSS VSS VSSA = VSS
M7 AD[1] AD[1] NC X AD[1] AD[1] AD[1]
M8 RVSD_NC CLK_VIEW NC X NC NC NC
M9 FLSH_CE# FLSH_CE# NC X NC NC NC
Table 13. Ball Number to Signal Mapping (Sheet 6 of 8) (Continued)
Population Options
Ball
Ref
82541xx
Pin
Name
82540EP
Pin Name
82562EZ
Pin Name
D
1
K
2
82541xx 82540EP 82562EZ Comments