Intel 82562EX, Руководство по конструкции

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82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide
15
The EEPROM access algorithm programmed into the 82541xx controller is compatible with most,
but not all, commercially available 3.3 V Microwire* interface, serial EEPROM devices, with 64 x
16 (or 256 x 16) organization and a 1 MHz speed rating. The 82541xx EEPROM access algorithm
drives extra pulses on the shift clock at the beginnings and ends of read and write cycles. The extra
pulses may violate the timing specifications of some EEPROM devices. In selecting a serial
EEPROM, choose a device that specifies “don't care” shift clock states between accesses.
Microwire EEPROMs that have been found to work satisfactorily with the 82541xx Gigabit
Ethernet Controller are listed in the following table:
SPI* EEPROMs that have been found to work satisfactorily with the 82541xx device are listed in
Table 9 . SPI* EEPROMs must be rated for a clock rate of at least 2 MHz.
3.3.3 EEPROM Map Information
Table 10 lists the EEPROM map for the 82541xx Gigabit Ethernet Controller.
NOTE: Full manageability provided.
Table 8. Microwire 64 x 16 Serial EEPROMs
Manufacturer Manufacturer's Part Number
Atmel AT93C46
1
Catalyst CAT93C46
1,2
1. No manageability provided.
2. Revision H is not supported. Product die revision letter is marked on top of the package as a suffix to the production data
code (e.g., AYWWH.)
Table 9. SPI* Serial EEPROMs for 82541xx Controller
Application Manufacturer
Manufacturer's Part
Number
ASF 1.0 or IMPI pass through ATMEL AT25040
ASF 2.0 or IMPI advanced pass through ATMEL AT25080
Table 10. 82541xx EEPROM Memory Layout
00h
3Fh
HW/SW Reserved Area
40h
FFh
ASF and Legacy
Manageability
100h
19F
Manageability Packet
Filter Data
1A0
...
EEPROM END Loadable
Manageability Firmware
Code